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Issue Date	Title / Author(s) / Citation	File
2011-04	Novel U-Shape Resistive Random Access Memory Structure for Improving Resistive Switching Characteristics Ryoo, Kyung-Chang; Oh, Jeong-Hoon; Jeong, Hongsik; Jung, Sunghun; Park, Byung-Gook JAPANESE JOURNAL OF APPLIED PHYSICS; Vol.50 4; -	DOI
2016-04	Diode-type NAND flash memory cell string having super-steep switching slope based on positive feedback Joe, Sung-Min; Kang, Ho-Jung; Choi, Nagyong; Kang, Myounggon; Park, Byung-Gook; Lee, Jong-Ho IEEE Transactions on Electron Devices, Vol.63 No.4, pp.1533-1538	DOI
2016-07	Improvement of Characteristics with a Sub-5 nm Ge-Doped Silicon Nitride Layer in Charge Trap Flash Memory Cells Li, Dong Hua; Kim, Wandong; Shim, Won Bo; Park, Se Hwan; Kim, Yoon; Lee, Gil Sung; Kim, Doo-Hyun; Lee, Jung Hoon; Yun, Jang-Gn; Cho, Seongjae; Park, Il Han; Lee, Jong-Ho; Shin, Hyungcheol; Park, Byung-Gook Nanoscience and Nanotechnology Letters, Vol.8 No.7, pp.577-580	DOI
2016-08	A 1T-DRAM cell based on a tunnel field-effect transistor with highly-scalable pillar and surrounding gate structure Kim, Hyungjin; Park, Byung-Gook Journal of the Korean Physical Society, Vol.69 No.3, pp.323-327	DOI
2016-08	Asymmetric dual-gate-structured one-transistor dynamic random access memory cells for retention characteristics improvement Kim, Hyungjin; Lee, Jong-Ho; Park, Byung-Gook Applied Physics Express, Vol.9 No.8, pp.084201-084201	DOI
2016-08	Elimination of the gate and drain bias stresses in I-V characteristics of WSe2 FETs by using dual channel pulse measurement Park, Jun-Mo; Cho, In-Tak; Kang, Won-Mook; Park, Byung-Gook; Lee, Jong-Ho Applied Physics Letters, Vol.109 No.5, p. 053503	DOI
2016-09	Novel program method of string select transistors for layer selection in channel-stacked NAND flash memory Kwon, Dae Woong; Kim, Wandong; Kim, Do-Bin; Lee, Sang-Ho; Seo, Joo Yun; Choi, Eunseok; Cho, Gyu Seog; Park, Sung-Kye; Lee, Jong-Ho; Park, Byung-Gook IEEE Transactions on Electron Devices, Vol.63 No.9, pp.3521-3526	DOI
2018-08	Dual Functions of V/SiOx/AlOy/p++Si Device as Selector and Memory Kim, Sungjun; Lin, Chih-Yang; Kim, Min-Hwi; Kim, Tae-Hyeon; Kim, Hyungjin; Chen, Ying-Chen; Chang, Yao-Feng; Park, Byung-Gook Nanoscale Research Letters, 13(1):252	view file DOI
2019-06	Ge Condensation Process for High ON/OFF Ratio of SiGe Gate-All-Around Nanowire Tunnel Field-Effect Transistor Lee, Ryoongbin; Lee, Junil; Kim, Sangwan; Lee, Kitae; Kim, Sihyun; Kim, Soyoun; Choi, Yunho; Park, Byung-Gook 2019 SILICON NANOELECTRONICS WORKSHOP (SNW), pp.51-52	DOI
2019-06	Comparison of switching characteristics of HfOx RRAM device with different switching layer thicknesses Lee, Dong Keun; Kim, Min-Hwi; Bang, Suhyun; Kim, Tae-Hyeon; Choi, Yeon-Joon; Kim, Sungjun; Cho, Seongjae; Park, Byung-Gook 2019 SILICON NANOELECTRONICS WORKSHOP (SNW), pp.69-70	DOI
2019-06	Improved Gradual Reset Phenomenon in SiNx-based RRAM by Diode-Connected Structure Kim, Min-Hwi; Bang, Suhyun; Kim, Tae-Hyeon; Lee, Dong Keun; Kim, Sungjun; Cho, Seongjae; Park, Byung-Gook 2019 SILICON NANOELECTRONICS WORKSHOP (SNW), pp.65-66	DOI
2019-06	A systematic model parameter extraction using differential evolution searching Chang, Jeesoo; Oh, Min-Hye; Park, Byung-Gook 2019 SILICON NANOELECTRONICS WORKSHOP (SNW), pp.81-82	DOI
2019-09	Transient Simulation of Field-Effect Biosensors : How to Avoid Charge Screening Effect Kim, Kyoung Yeon; Park, Byung-Gook 2019 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD 2019), pp.182-184	DOI
2020-06	Local Variation-Aware Transistor Design through Comprehensive Analysis of Various V-dd/Temperatures Using Sub-7nm Advanced FinFET Technology Kim, Soyoun; Kim, Seung Kwon; Yamaguchi, Taiko; Kim, Jae Chul; Park, Byung-Gook; Yasuda-Masuoka, Yuri; Kwon, S. D. 2020 IEEE SYMPOSIUM ON VLSI TECHNOLOGY, p. 9265089	DOI
2020-06	Study on Etch Slope in Fin and Source/Drain Etch Process of Vertically-Stacked Nanosheet Gate-All-Around MOSFET Kim, Sihyun; Lee, Kitae; Park, Byung-Gook 2020 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW), pp.99-100	DOI
2020-06	Influence of Gate to Drain Underlap on Negative Differencial Resistance in Ferroelectric FET Lee, Kitae; Kim, Sihyun; Park, Byung-Gook 2020 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW), pp.95-96	DOI
2020-06	Design and Analysis of Core-Gate Shell-Channel 1T DRAM Ansari, Md Hasan Raza; Lee, Jae Yoon; Cho, Seongjae; Park, Byung-Gook 2020 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW), pp.25-26	DOI
2020-06	Highly scalable 4F(2) cell transistor for future DRAM technology Min, Kyung Kyu; Hwang, Sungmin; Lee, Jong-Ho; Park, Byung-Gook 2020 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW), pp.81-82	DOI
2021-04	Core-Shell Dual-Gate Nanowire Synaptic Transistor with Short/Long-Term Plasticity Ansari, Md Hasan Raza; Kim, Daehwan; Cho, Seongjae; Lee, Jong-Ho; Park, Byung-Gook 2021 5TH IEEE ELECTRON DEVICES TECHNOLOGY & MANUFACTURING CONFERENCE (EDTM)	DOI
2021-06	Neuron Circuit Using Current Mirror to Ensure High Output Linearity in SNNs Park, Kyungchul; Hwang, Sungmin; Chang, Jeesoo; Min, Kyungkyu; Jang, Taejin; Jeon, Bosung; Cha, Youngsan; Lee, Jong-Ho; Park, Byung-Gook 2021 SILICON NANOELECTRONICS WORKSHOP (SNW), pp.67-68	DOI
2021-06	Guideline of optimum interfacial layers in metal-ferroelectric-insulator-semiconductor structure for gate stack and ferroelectric tunnel junction Yu, Junsu; Min, Kyung Kyu; Kim, Yeonwoo; Kwon, Daewoong; Park, Byung-Gook 2021 SILICON NANOELECTRONICS WORKSHOP (SNW), pp.29-30	DOI
2021-08	Effects of Pillar Conditions on DC/AC Characteristics of Tunnel Field-effect Transistor with Vertical Structures Yu, Junsu; Park, Byung-Gook; Kwon, Dae Woong JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, Vol.21 No.4, pp.241-246	DOI
2022-01	SiO2 Fin-Based Flash Synaptic Cells in AND Array Architecture for Binary Neural Networks Lee, Soochang; Kim, Hyeongsu; Lee, Sung-Tae; Park, Byung-Gook; Lee, Jong-Ho IEEE Electron Device Letters, Vol.43 No.1, pp.142-145	DOI
2022-01	Impact of interlayer insulator formation methods on HfOx ferroelectricity in the metal-ferroelectric-insulator-semiconductor stack Min, Kyung Kyu; Kwon, Seok Jin; Kim, Yeonwoo; Yu, Junsu; Lee, Jong-Ho; Park, Byung-Gook; Kwon, Daewoong Applied Physics Letters, Vol.120 No.1, p. 012901	DOI
2022-01	Ferroelectricity of pure HfOx in metal-ferroelectric-insulator-semiconductor stacks and its memory application Min, Kyung Kyu; Yu, Junsu; Kim, Yeonwoo; Kim, Chae Soo; Jang, Taejin; Hwang, Sungmin; Kim, Hyungjin; Lee, Jong-Ho; Kwon, Daewoong; Park, Byung-Gook Applied Surface Science, Vol.573, p. 151566	DOI
2022-04	Capacitor-Based Synaptic Devices for Hardware Spiking Neural Networks Hwang, Sungmin; Yu, Junsu; Lee, Geun Ho; Song, Min Suk; Chang, Jeesoo; Min, Kyung Kyu; Jang, Taejin; Lee, Jong-Ho; Park, Byung-Gook; Kim, Hyungjin IEEE Electron Device Letters, Vol.43 No.4, pp.549-552	DOI
2022-04	Lamination method for improved polarization-leakage current relation in HfO2-based metal/ferroelectric/insulator/semiconductor structure Kim, Yeonwoo; Min, Kyung Kyu; Yu, Junsu; Kwon, Daewoong; Park, Byung-Gook Semiconductor Science and Technology, Vol.37 No.4, p. 045001	DOI
2022-05	Thermal-Aware IC Chip Design by Combining High Thermal Conductivity Materials and GAA MOSFET Song, Young Suh; Tayal, Shubham; Rahi, Shiromani Balmukund; Kim, Jang Hyun; Upadhyay, Abhishek Kumar; Park, Byung-Gook 2022 5TH INTERNATIONAL CONFERENCE ON CIRCUITS, SYSTEMS AND SIMULATION (ICCSS 2022), pp.135-140	DOI
2022-05	Damage-Induced Ferroelectricity in HfOx-Based Thin Film Min, Kyung Kyu; Kim, Hyun-Min; Kim, Yeonwoo; Kim, Changha; Yu, Junsu; Lee, Jong-Ho; Park, Byung-Gook; Kwon, Daewoong IEEE Electron Device Letters, Vol.43 No.5, pp.713-716	DOI
2022-06	Investigation of Low-Frequency Noise Characteristics of Ferroelectric Tunnel Junction: From Conduction Mechanism and Scaling Perspectives Shin, Wonjun; Bae, Jong-Ho; Kwon, Dongseok; Koo, Ryun-Han; Park, Byung-Gook; Kwon, Daewoong; Lee, Jong-Ho IEEE Electron Device Letters, Vol.43 No.6, pp.958-961	DOI
2022-06	Effect of Program Error in Memristive Neural Network With Weight Quantization Kim, Tae-Hyeon; Kim, Sungjoon; Hong, Kyungho; Park, Jinwoo; Youn, Sangwook; Lee, Jong-Ho; Park, Byung-Gook; Kim, Hyungjin IEEE Transactions on Electron Devices, Vol.69 No.6, pp.3151-3157	DOI
2022-07	Highly Efficient Self-Curing Method in MOSFET Using Parasitic Bipolar Junction Transistor Shin, Wonjun; Koo, Ryun-Han; Hong, Seongbin; Kwon, Dongseok; Hwang, Joon; Park, Byung-Gook; Lee, Jong-Ho IEEE Electron Device Letters, Vol.43 No.7, pp.1001-1004	DOI
2022-07	Analog synaptic devices applied to spiking neural networks for reinforcement learning applications Kim, Jangsaeng; Lee, Soochang; Kim, Chul-Heung; Park, Byung-Gook; Lee, Jong-Ho Semiconductor Science and Technology, Vol.37 No.7, p. 075002	DOI
2022-07	Medium-Temperature-Oxidized GeOx Resistive-Switching Random-Access Memory and Its Applicability in Processing-in-Memory Computing Mohanan, Kannan Udaya; Cho, Seongjae; Park, Byung-Gook Nanoscale Research Letters, Vol.17 No.1, p. 63	DOI
2022-07	Medium-Temperature-Oxidized GeOx Resistive-Switching Random-Access Memory and Its Applicability in Processing-in-Memory Computing Kannan Udaya Mohanan; Cho, Seongjae; Park, Byung-Gook Nanoscale Research Letters,17(1):63	view file link
2022-09	4-bit Multilevel Operation in Overshoot Suppressed Al2O3/TiOx Resistive Random-Access Memory Crossbar Array Kim, Sungjoon; Park, Jinwoo; Kim, Tae-Hyeon; Hong, Kyungho; Hwang, Yeongjin; Park, Byung-Gook; Kim, Hyungjin Advanced Intelligent Systems, Vol.4 No.9, p. 2100273	DOI
2022-09	Fully integrated FET-type gas sensor with optimized signal-to-noise ratio for H2S gas detection Shin, Wonjun; Jeong, Yujeong; Hong, Seongbin; Jung, Gyuweon; Park, Jinwoo; Kim, Donghee; Park, Byung-Gook; Lee, Jong-Ho Sensors and Actuators, B: Chemical, Vol.367, p. 132052	DOI
2022-10	Impact of the leakage current of an AND-type synapse array on spiking neural networks Jeon, Bosung; Song, Seunghwan; Hwang, Sungmin; Jang, Taejin; Park, Kyungchul; Park, Jonghyuk; Lee, Jong-Ho; Park, Byung-Gook Solid-State Electronics, Vol.196, p. 108407	DOI
2022-10	Highly-packed self-assembled graphene oxide film-integrated resistive random-access memory on a silicon substrate for neuromorphic application Choi, Hyun-Seok; Lee, Jihye; Kim, Boram; Lee, Jaehong; Park, Byung-Gook; Kim, Yoon; Hong, Suck Won Nanotechnology, Vol.33 No.43, p. ac805d	DOI
	Highly Linear Analog Spike Processing Block Integrated With an AND-Type Flash Array and CMOS Neuron Circuits Lee, Kyu-Ho; Kwon, Dongseok; Woo, Sung Yun; Ko, Jong Hyun; Choi, Woo Young; Park, Byung-Gook; Lee, Jong-Ho IEEE Transactions on Electron Devices	DOI