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Showing results 1 to 9 of 9

Issue Date	Title / Author(s) / Citation	File	Altmetrics
2008-02	Enthalpy probe measurements and three-dimensional modelling on air plasma jets generated by a non-transferred plasma torch with hollow electrodes Kim, Keun Su; Park, Jin Myung; Choi, Sooseok; Kim, Jongin; Hong, Sang Hee J. Phys. D: Appl. Phys. 41 065201	DOI
2012-06	Characteristics of Gate-All-Around Hetero-Gate-Dielectric Tunneling Field-Effect Transistors Lee, Jae Sung; Choi, Woo Young; Kang, In Man Japanese Journal of Applied Physics, Vol.51 No.6S, p. 06FE03	DOI
2014-03	Effects of abnormal cell-to-cell interference on p-type floating gate and control gate NAND flash memory Kim, Yong Jun; Kang, Jun Geun; Lee, Byungin; Cho, Gyu-Seog; Park, Sung-Kye; Choi, Woo Young Japanese Journal of Applied Physics, Vol.53 No.4S, p. 04ED12	DOI
2014-11	Disturbance characteristics of charge trap flash memory with tunneling field-effect transistor Xi, Ning; Cho, Eou-Sik; Choi, Woo Young; Choi, Il Hwan Japanese Journal of Applied Physics, Vol.53 No.11, p. 114201	DOI
2017-01	A sub-0.5 V operating RF low noise amplifier using tunneling-FET Jhon, Hee-Sauk; Jeon, Jongwook; Kang, Myunggon; Choi, Woo Young Japanese Journal of Applied Physics, Vol.56 No.2, p. 020303	DOI
2017-01	Effects of drain bias on the statistical variation of double-gate tunnel field-effect transistors Choi, Woo Young Japanese Journal of Applied Physics, Vol.56 No.4S, p. 04CD01	DOI
2017-02	Influence of line-edge roughness on multiple-gate tunnel field-effect transistors Choi, Woo Young Japanese Journal of Applied Physics, Vol.56 No.4S, p. 04CD06	DOI
2017-03	Monolithic three-dimensional tunnel FET-nanoelectromechanical hybrid reconfigurable logic circuits Kim, Seung Kyu; Choi, Woo Young Japanese Journal of Applied Physics, Vol.56 No.4S, p. 04CD12	DOI
2017-07	Improved compact model for double-gate tunnel field-effect transistors by the rigorous consideration of gate fringing field Kim, Sangwan; Choi, Woo Young Japanese Journal of Applied Physics, Vol.56 No.8, p. 084301	DOI

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