High quality GaP and InP growth on Si (001) substrates by MOCVD

Abstract

High-quality epitaxial growth of III-V on silicon substrates has been of great interest for many years due to because of the potential for monolithic integration of III-V based devices with Si metal-oxide semiconductor (MOS) integrated circuits and high performance and low power logic devices. Particularly, integration of III-V on Si can open up opportunities for new functionalities and multiple integration platforms, such as terahertz electronics, optoelectronics, integrating logic and communication platforms on the same Si wafer. In this dissertation, the epitaxial growth of InP layers on Si (001) substrates by selective area growth (SAG) has been studied in order to explore the potential applications as mentioned before. High quality InP layers were grown using a thin GaP buffer layer in SiNx trenches on Si (001) substrates. There are three main challenges for growth of high quality epitaxial layers. The first challenge is the high defect density in the epitaxial layers due to the large lattice mismatch between InP and the Si substrates. The second is the large difference in thermal expansion coefficient between InP and the Si substrates or SiNx mask in SAG. Last one is the generation of polar/non-polar interfaces between InP and Si substrates. The main focus of this work is to understand the defect formation mechanism as well as to develop solutions for defect reduction and to grow InP layers having extremely flat top surface for CMOS applications without CMP process. A thin GaP buffer layer is used as the intermediate layer between the InP and the Si substrates to alleviate the large lattice mismatch and to facilitate the InP nucleation. We find the optimized growth condition of GaP layers on exact Si (001) substrate through a multi-step MOCVD process to achieve such high quality GaP/Si (001) template substrates by planar method. We have investigated the generation process of low defects in GaP layers grown on Si substrates by FME. It was found that there were optimized growth conditions as growth temperature, V/III ratio and growth rate. RMS roughness is 2.8 nm from the optimized growth conditions. InP epilayers were grown on Si substrates using buffer layers of GaP. AFM, SEM and TEM examination results showed that GaP is a proper material as a buffer layer, and that its optimum thickness is about 3~5nm. TEM observation showed that the inserted InGaAs strained layers were very helpful to reduce the surface roughness and defect reduction. It also confirmed that GaP acted as a buffer to alleviate the lattice mismatch between InP and Si. The best AFM roughness obtained from inserted InGaAs strained layers was 2.1nm for 5ⅹ5 μm2. Next, we also propose a new scheme of SiNx mask for SAG process to grow InP layers with high quality and flat top surface by applying to mask with etched Si surfaces and rounded top shape SiNx. The extremely flat InP top surface is obtained by the optimized SiNx mask for SAG. In last part, we investigated SAG of InP layers on patterned Si substrates with InP/GaP buffer layers at various growth temperatures ranging from 500 °C to 650 °C. In order to grow high quality InP, a thin GaP buffer layer was grown on stepped sidewall surfaces of etched Si. The different growth temperature resulted in different top surfaces. The high quality InP layer with smooth surface can be attributed to the dislocation necking effect together with the formation of void. Finally we demonstrated the formation of InGaAs/InP heterostructures using the suggested InP templates, which can be used in applications of electronic devices.