Fabrication and characterization of 3D stacked crossbar array employing a rectifying RRAM device

Abstract

Resistive switching random access memory (RRAM) is becoming a strong contender as the replacement of NAND flash memory. When it is implemented in crossbar array (CBA) configuration, which does not require the employment of transistor as its selector, it becomes very cost-competitive especially in vertically integrated form. However, the highly parallel memory cell architecture of CBA gives such a serious interference problem among the cells, originated from the undesirable sneak currents flow through the unselected cells. Such a sneak current has been the main challenge that hampers the realization of RRAM to a high density storage (class) memory. Therefore, aside from enhancing the performance of a RRAM device itself, active researches on enhancing the selector performance have been reported in recent years. Nevertheless, the design criteria for such selectors have relied on the reading margin evaluation based on the preceding studies on the sneak currents analysis during read operation. As the first part of this study, it is revealed that the sneak current issue needs to be considered more seriously even during writing margin evaluation, which have been relatively overlooked compared with the reading margin evaluation. Being further improved from the preceding sneak currents analysis, sneak current effects are even more thoroughly examined combined with the effect of resistances of memory cells and interconnection wires, and operation parameter of the device. As a result, it is shown that further intensified voltage division effect of interconnect wires occurs due to the involvement of sneak currents through the neighboring cells. Moreover, it is also verified that the voltage applied to the unselected cells during the write operation may critically disturb those cells, incurring additional writing margin problem. The study is proposing an analytical model dealing with such sneak currents involved in the writing margin issue, provided with validation of the model through a HSPICE circuit simulation. Furthermore, the analysis is applied to a few typical resistive switching systems accompanying rectifying characteristic, mainly based on the aim of mitigating such sneak currents problem in a high density CBA. Complimentary resistive switching (CRS) is one of the most promising system, wherein resistive switching occurs between two different high resistance states. Based on this system, every unselected cell in a crossbar array except for a selected cell features high resistance irrespective of their status, therefore, sneak currents through the unselected cells can be effectively suppressed. Transition metal oxides (TMO) have been known to be the promising resistive switching materials owing to their naturally inherent high non-stoichiometry. Resistive switching in these materials have been attributed to the migration of ionic defects according to electric field. Making use of the ionic resistive switching at conducting filaments ruptured region of a single layered TMO, an effective way of achieving a CRS just by applying a series of electrical stimulus is suggested. Combined analysis upon the time-transient current during the voltage pulsing and the resistance status obtained in the voltage sweep mode confirms and gives the detailed physical reasoning and kinetic behaviors for the desired phenomenon in the system. It is also proven that, through a series of comparison with the samples of different materials and stacks, such property basically requires the finite amount of defects, which can be readily achieved especially in the transition metal oxides involving phase transition into the metallic phase (Magnéli), such as TiO2 and WO3. However, in order for an integration of 3 dimensional-(3D-) RRAM, higher selectivity than that of the CRS was required. Therefore, a diode selector was adopted to introduce an excellent rectifying property to a resistive switching memory, resulting in a stacked structure of one-diode one-resistance switching memory (1D1R). TiO2 as the main functioning oxide for both the diode and the memory comprising 1D1R is fabricated at room temperature (RT), optimized for stacking of the multiple planar crosspoint structures being free from the thermal disruption issues over the repetitive stacking procedures. The RT fabricated diode showed a rectification ratio improved as much as 103 from the preceding diode devices for ReRAM selector applications. As the rectifying property is enhanced with the decreasing electrode area, the maximum rectifying ratio of 8.4x108 (at a reading voltage of 2V) even in the low resistance state (LRS) of the resistive switching memory, is obtained alongside a reliable on/off window of 103-4 based on a filamentary unipolar resistive switching (URS) in 2x2 μm2 crosspoint 1D1R device. Random access memory operation of erasing, programming, and reading a selected cell being uninterrupted by sneak currents from neighboring cells was demonstrated in a double-layered 3D 4x4 crossbar array. Furthermore, a 2bit-memory operation with little overlaps among three LRS states and one HRS was performed, further shrinking the cell size down to F2, where F is the minimum feature size.