A Low-power Data Interface Circuit and Analog Data Converter for Biomedical Device

Abstract

In this study, a low-power referenceless clock and data recovery (CDR) circuit and cyclic analog data converters (ADC) were implemented and verified by standard CMOS technology for biomedical systems.

A Biomedical system performs signal acquisition, amplification, filtering and also undertakes quantization and neural stimulation. It needs to be small in size and powerefficient. First of all, the heat in proportion to power consumption generated by the circuit must be considered, in order to avoid the possibility of tissue damage. The battery size can be reduced by low power consumption in a battery-powered biomedical system. Also the biomedical system should small for improving bio-compatibility.

In this study, a low-power referenceless CDR is designed and validated in 0.18μm standard CMOS technology. It adopts clock-edge modulation and a voltage-controlled oscillator based on a relaxation oscillator. Our CDR has an input data-rate of 200kbps to 10Mbps when the supply voltage is 0.7V, and operates at up to 24MHz with a supply voltage of 1.0V. The bit error-rate of our CDR is lower than 10^-13. The energy per bit is only 0.8pJ/bit, even though the circuit is implemented in a 0.18μm CMOS technology.

The demand for low-power low-voltage analog-to-digital converters (ADCs) for biomedical systems has recently grown dramatically. Among several ADC architectures, the cyclic ADC achieves high resolution with small chip area and low power, because it performs a conversion cyclically by repeated use of a single gain stage.

Our first prototype which is a 10-bit cyclic ADC adopts the comparator-based switched-capacitor (CBSC) technique, for the first time, so as to compensate for the technology scaling and to reduce power consumption by eliminating the need for high gain op-amps. A boosted preset voltage is also introduced to improve the conversion rate without consuming more power. The ADC operates at 2.5MS/s, and near the Nyquist-rate, the prototype has a signal-to-noise and distortion ratio (SNDR) of 55.99 dB and a spurious-free dynamic-range (SFDR) of 66.85 dB. The chip was fabricated in 0.18μm CMOS and it has an active area of 0.146mm2 and consumes 0.74mW from a 1.8V supply. A proposed second cyclic ADC which has a 12-bit resolution with CBSC adopts the multi-level input tracking boosted preset voltage scheme, asynchronous clocking scheme and adjustable threshold voltage in the comparator. The multi-level input tracking preset voltages scheme can achieve shorter coarse conversion time than the conventional one. Moreover, by reusing the sub-ADC in the MDAC, the proposed input tracking preset voltages scheme does not needed additional circuits. An asynchronous clocking scheme only synchronizes the sampling signal. After the end of the conversion time, sleep mode is maintained until the next signal of sample and helps reduce the power consumption because the current source and comparator are power down. The scheme of adjustable threshold voltage in the comparator reduces the coarse conversion time. Moreover, the overshoot is reduced which means that the fine conversion time is also shortened. The ADC operates at 3MS/s, and near the Nyquist-rate, the simulation results show a signalto- noise and distortion ratio (SNDR) of 64.9dB and a spurious-free dynamic-range(SFDR) of 69.7dB. The chip was designed in 0.18μm CMOS and it has an area of 0.23mm2 and consumes 1.6mW from a 1.8V supply.