Performance Improvement of Memory System with LPDDR2-NVM

Abstract

Typical memory systems have used a synchronous random access memory (SRAM), a dynamic random access memory (DRAM), and a NAND flash in a cache, main memory, and storage, respectively. However, these traditional memory devices have limitations such as volatility, low density, and high leakage power. Therefore, emerging non-volatile memory (NVM) technologies such as phase change memory (PCM), spin-torque transfer random access memory (STT-RAM), and resistive random access memory (RRAM) are considered as an alternative of traditional memory devices due to its non-volatility, high density, and low-power. These numerous benefits of emerging NVMs motivate researchers to investigate the adoption of NVMs to the memory hierarchy. Low power double data rate 2 non-volatile memory (LPDDR2-NVM) has been deemed the standard interface to connect NVMs because the characteristics of emerging NVMs are different to the traditional memory devices. The operation of LPDDR2-NVM is not same as the conventional DRAM, but most of the previous literature does not consider or overlook this standard interface. This dissertation proposes system-level optimization methods to maximize the performance of memory system with LPDDR2-NVM. To this end, we first implement an LPDDR2-NVM prototype to extract parameters of memory system, and then we implement a system-level simulator that reflects the realistic parameters. Second, we analyze the effect of row buffer architecture on the performance of the memory system though the intensive evaluation. Based on clues from evaluation, we propose a system-level method that improves performance memory system by reforming the way of interfacing LPDDR2-NVM. We also present the limitation of static row buffer architecture and propose a system-level method that mimics reconfigurable row buffer architecture.