S-Space College of Engineering/Engineering Practice School (공과대학/대학원) Dept. of Electrical and Computer Engineering (전기·정보공학부) Theses (Ph.D. / Sc.D._전기·정보공학부)
Analysis on Characteristics and Trapping Mechanism of Trap Sites inside Dielectric or Drain Causing Random Telegraph Noise in Trap-Assisted Tunneling GIDL
Trap-assisted 터널링 GIDL 전류에서 RTN을 발생시키는 절연체 또는 실리콘 내부 트랩 사이트 특성과 트랩핑 메커니즘 분석
- 공과대학 전기·컴퓨터공학부
- Issue Date
- 서울대학교 대학원
- Trap-assisted tunneling GIDL current RTN; trap-detrap site; distance between two trap sites; trapping mechanism
- 학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 2. 신형철.
- Variable retention time (VRT) phenomenon is one of the main sources which degrade the retention time of DRAM cell, and this phenomenon becomes recently serious issue in DRAM cell transistor. Through various researches, it is revealed that the origin of VRT phenomenon is gate induced drain leakage (GIDL) current random telegraph noise (RTN). Thus, comprehensive analyses on traps causing GIDL current RTN should be implemented in order to accurately understand VRT phenomenon. So far, researches on GIDL current RTN in band-to-band tunneling (BTB) current region have been mainly conducted. The characteristics of trap-detrap site causing RTN in BTB GIDL current have been analyzed in various literatures based on the GIDL RTN measurement data. However, with device and supply voltage scaling, researches on GIDL current RTN in TAT region become important topics since GIDL current through trap-assisted tunneling (TAT) mainly flows in the low supply voltage region. And, on the contrast to other current RTN, two trap sites (trap-detrap site and generation-recombination site) cause RTN in TAT GIDL current, which suggests that more characteristics should be accurately analyzed. Nevertheless, there are great lack of the researches on TAT GIDL current RTN and several weaknesses for accurately extracting the characteristics of trap sites.
In this thesis, two trap sites causing GIDL current RTN in TAT current region were physically analyzed. The depth and energy level of traps were extracted based on the measurement data in TAT GIDL current RTN in case of trap detrap site inside silicon dioxide. And, the method for extracting the distance between two trap sites was proposed and the distance between two trap sites was actually extracted using the ratio between two TAT GIDL current levels and proper effective permittivity of two different materials.
Second, trapping mechanism was also determined using activation energy comparison of time constants. And, RTN in GIDL current was for the first time measured as a result of electron trapping from conduction band rather than from valence band.
The GIDL current RTN in Buried-Gate CAT (BCAT) array which is used as DRAM cell transistor was actually measured. Especially, the method for extracting the trap characteristics was explained as trap-detrap site was located inside silicon (drain region) as well as conventional trap-detrap sites located in the dielectric or at interface for the first time. The physical characteristics of two trap sites was actually analyzed in case of trap-detrap site inside drain region based on the measurement data of RTN in TAT GIDL current. The researches explained in this thesis provide the insight for understanding and analyzing the GIDL RTN in TAT current region. Moreover, these can be useful in order to understand VRT phenomenon and research the method for reducing VRT phenomenon.