Channel-Stacked NAND Flash Memory with High-κ Charge Trapping Layer for High Scalability

Abstract

Exploding demands for mobile devices induce the drastic expansion of the market of NAND flash memory as high density storage devices. Three-dimensional (3D) NAND flash memory paved a new way of increasing the memory capacity by stacking cells in three-dimension. For stacked NAND flash memory, the thickness of ONO (memory dielectric layers) is a roadblock in scaling-down of the minimum feature size, because channel diameter can be scaled down to < 20 nm. However, it is challenging to reduce the thickness of oxide-nitride-oxide (ONO) layer, since the charge trapping properties degrade when the Si3N4 is made thinner. .In this thesis, the channel stacked NAND flash memory array (CSTAR) with high-κ charge trapping layer for high scalability is proposed. To adopt high-κ layer into 3D NAND, its memory characteristics were evaluated with capacitors and gate-all-around flash memory devices. Finally, 4-layer channel stacked memory with high-κ layer was successfully fabricated and characterized. Recent trend of nonvolatile memories are introduced and the overview of 3D stacked NAND flash memory technology is presented in Chapter 1 and 2. In Chapter 3, the memory characteristics of high-κ layer were evaluated with fabricated capacitors and flash memory devices. In Chapter 4, fabrication process and electrical characteristics of CSTAR with high-κ are shown. With the comparison with previous works using ONO layer, CSTAR with high-κ is evaluated. In Chapter 5, the novel operation method of CSTAR is presented. Using TCAD and measurement, a newly designed operation method is verified