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Design of Injection-Locked PLL with Digital Calibration of Frequency Error and Path Mismatch
주파수 오류 및 패쓰 미스매치의 디지털 보정 회로를 포함한 주입 고정 위상 동기화 루프의 설계

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dc.contributor.advisor정덕균-
dc.contributor.author김성우-
dc.date.accessioned2017-07-13T07:20:26Z-
dc.date.available2017-07-13T07:20:26Z-
dc.date.issued2017-02-
dc.identifier.other000000141455-
dc.identifier.urihttp://hdl.handle.net/10371/119265-
dc.description학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2017. 2. 정덕균.-
dc.description.abstractA novel injection technique for the extension of the noise-filtering band-width is proposed to filter out an oscillator’s noise in high frequency region. In addition, injection-locked phase-locked loops (IL-PLL) are proposed to mini-mize a frequency error fERR and a path mismatch pERR. Here, fERR is defined as the frequency difference between the free-running frequency of an oscillator and the desired frequency. Besides, pERR includes a non-ideal delay and a de-vice mismatch. This thesis insists two IL-PLLs using different calibration loops.
First, an IL-PLL using a charge-stored complementary switch (CSCS) injec-tion technique is proposed. The IL-PLL exhibits a wider locking range com-pared to other conventional IL-PLLs, owing to the improvement of the injection effect by the proposed CSCS. A frequency error calibration loop and a device mismatch calibration loop force the frequency error to be zero to minimize jit-ter and reference spur. The prototype chip fabricated in 65-nm CMOS technol-ogy achieves a 285-fsrms integrated jitter at 3.328 GHz from the reference clock of 52 MHz while consuming 7.16 mW. The figure-of-merit of the IL-PLL is −242.4 dB.
Second, an IL-PLL offering an excellent spur level with a time-division dual calibration (TDDC) scheme is proposed. The TDDC employs a replica delay cell in the injection-locked oscillator to detect and eliminate both a frequency error and a path mismatch. Robustness of the TDDC is verified over multiple samples by varying the supply voltage. With the TDDC enabled, the prototype chip fabricated in 65-nm CMOS technology achieves the spur reduction of 23 dBc, resulting in the spur level of -65 dBc. The integrated jitter at 2.5 GHz from the reference clock of 156.25 MHz is 198 fsrms while consuming 13.5 mW from a 1.1 V supply. The figure-of-merit of the IL-PLL is ‒242.8 dB.
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dc.description.tableofcontentsCHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 THESIS ORGANIZATION 3
CHAPTER 2 BASIC INJECTION-LOCKED OSCILLATOR 5
2.1 INJECTION LOCKING 5
2.2 APPLICATIONS 7
2.2.1 INJECTION-LOCKED FREQUENCY DIVIDER 8
2.2.2 INJECTION-LOCKED FREQUENCY MULTIPLIER 12
2.2.3 INJECTION-LOCKED CLOCK MULTIPLIER 16
2.3 ANALYSIS 18
2.3.1 INJECTION LOCKING RANGE 18
2.3.2 PHASE DOMAIN RESPONSE 22
2.3.2 JITTER TRACKING BANDWIDTH 28
2.3.4 PHASE NOISE IN REALIGNED OSCILLATOR 30
2.4 DESIGN ISSUES IN INJECTION-LOCKED CLOCK MULTIPLIER 36
2.4.1 FALSE LOCK 36
2.4.2 PHASE NOISE PERFORMANCE 37
2.4.3 DETERMINISTIC JITTER AND SPUR 38
2.5 PRIOR ARTS 41
2.5.1 INJECTION-LOCKED PHASE-LOCKED LOOP 41
2.5.2 HIGH-RESOLUTION TIME-TO-DIGITAL CONVERTER 45
2.5.3 REPLICA OSCILLATOR 47
2.5.4 GATED PULSE 48
2.5.5 REPLICA DELAY CELL 50
CHAPTER 3 IL-PLL WITH CSCS INJECTION TECHNIQUE 52
3.1 OVERVIEW 52
3.2 CHARGE-STORED COMPLEMENTARY SWITCH INJECTION TECHNIQUE 53
3.3 FREQUENCY/MISMATCH CALIBRATION LOOP 61
3.4 CIRCUIT IMPLEMENTATION 63
3.5 MEASUREMENT RESULTS 70
CHAPTER 4 IL-PLL WITH TIME-DIVISION DUAL CALIBRATION 76
4.1 OVERVIEW 76
4.2 TIME-DIVISION DUAL CALIBRATION 80
4.3 CIRCUIT IMPLEMENTATION 83
4.5 MEASUREMENT RESULTS 88
CHAPTER 5 CONCLUSION 96
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dc.formatapplication/pdf-
dc.format.extent2431733 bytes-
dc.format.mediumapplication/pdf-
dc.language.isoen-
dc.publisher서울대학교 대학원-
dc.subjectCharge-stored complementary switch-
dc.subjectfrequency synthesizer-
dc.subjectinjection-locked oscillator-
dc.subjectphase-locked loop-
dc.subject.ddc621-
dc.titleDesign of Injection-Locked PLL with Digital Calibration of Frequency Error and Path Mismatch-
dc.title.alternative주파수 오류 및 패쓰 미스매치의 디지털 보정 회로를 포함한 주입 고정 위상 동기화 루프의 설계-
dc.typeThesis-
dc.description.degreeDoctor-
dc.citation.pages103-
dc.contributor.affiliation공과대학 전기·컴퓨터공학부-
dc.date.awarded2017-02-
Appears in Collections:
College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Theses (Ph.D. / Sc.D._전기·정보공학부)
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