A STUDY ON LOW-PHASE-NOISE 77-GHZ CMOS TRANSMITTER FOR FMCW RADAR

Abstract

This thesis presents design methodology and experimental verification of a low-phase-noise 77-GHz CMOS FMCW (Frequency Modulated Continuous Wave) radar transmitter. It is quite difficult to design a low-phase-noise signal generator at millimeter-wave frequencies in CMOS because gain of CMOS transistors is extremely low at those frequencies. When using a frequency multiplier, it is relatively advantageous to design a low-phase-noise signal source because a VCO can be designed at lower frequency band where gain of active devices is high. When using multiple stage frequency multipliers to achieve low-phase-noise performance, the operating frequency range can be reduced and DC power consumption can be increased. Therefore, in this thesis, two methods for realizing 77-GHz CMOS low-phase-noise signal source have been proposed. One method is to combine a ×6 frequency multiplier and a 12.8-GHz FMCW signal generator. In this case, a VCO, an injection-locked VCO buffer, a ×3 frequency multiplier (tripler), and a ×2 frequency multiplier (doubler) constituting the 77-GHz signal generator are designed as a four-stage coupled injection-locked oscillator (ILO) chain which is oscillated and injected into the output signal of the preceding stage. The VCO used in the 12.8-GHz PLL (phase locked loop) was designed using linearized transconductance (LiT: Linearized Transconductance) technology to have low phase noise characteristics and was designed to be simpler than the existing LiT VCO using a 3:2 transformer. Since the PLL is designed as the integer-N type, an external frequency modulated triangular reference signal must be injected into the phase frequency detector (PFD) of the PLL to generate the FMCW signal. The fabricated transmitter chip supports FMCW output signals in the 76.81-77.95 GHz band when supplied with the external reference triangular signal from 50.00 to 50.75 MHz. The RF output power is about 8.9 dBm and consumes 116.7 mW of DC power. The measured phase noise is -91.16 dBc/Hz at the 1-MHz offset of the 76.81-GHz carrier frequency, which is the lowest phase noise characteristic of the previously announced 77-GHz CMOS transmitter and transceiver. A transmitter module for 77-GHz radar performance measurement was fabricated by combining the transmitter chip with the on-chip feeder that can solve the millimeter-wave packaging problem. The other is a method of combining a ×28 frequency multiplier and a 2.75-GHz FMCW signal generator. As in the previous method, the VCO, a ×7 multiplier, and two ×2 multipliers constituting the 77-GHz signal generator are each designed as a 4-stage ILO chain. The VCO used in the 2.75-GHz PLL is designed as a class-C type that improves the startup problem to have low-phase-noise characteristics. As in the previous case, an integer-N type PLL is used. The fabricated transmitter chip supports FMCW output signals in the 76.26-78.23 GHz band when supplied with the external reference triangular signal from 42.55 to 43.65 MHz. The RF output power is about -18 dBm and consumes 195.4 mW of DC power. The measured phase noise is -93.64 dBc/Hz at the 1-MHz offset of the 78.13-GHz carrier frequency, which is even lower phase noise characteristic than the ×6 frequency multiplier based transmitter chip.