Study on Random Telegraph Noise in Nano-wire and Saddle Device Using Simulation

Abstract

A 70-Å nano-wire field-effect transistor (FET) for sub-10-nm CMOS technology is designed and simulated in order to investigate the impact of an oxide trap on random telegraph noise (RTN) in the device. It is observed that the drain current fluctuation (ΔID/ID) increases up to a maximum of 78 % due to the single electron trapping. In addition, the effect of various trap positions on the RTN in the nano-wire FET is thoroughly analyzed at various drain and gate voltages. As the drain voltage increases, the peak point for the ΔID/ID shifts toward the source side. The distortion in the electron carrier density and the conduction band energy when the trap is filled with an electron at various positions in the device supports these results. Random telegraph noise (RTN) magnitude in the Gate Induced Drain Leakage (GIDL) current of Saddle MOSFET, a promising candidate for high-density DRAM applications, is analyzed using three-dimensional simulation TCAD. We simulated the RTN magnitude in GIDL with various trap positions. The distortion in the electron field distribution when the trap is filled with an electron at various positions in the device supports these results.