Analysis of Variable Retention Time Using Random Telegraph Noise Model in DRAM Cell

Abstract

According to the JEDEC standards, a dynamic random access memory (DRAM) cell must keep its information/charge for a minimum time of 64 ms. Although the DRAM companies use an enough guard band for the retention time, intermittent retention failures occur due to bit-level fluctuation of retention time. This random telegraph signal (RTS)-like fluctuation of data retention time called variable retention time (VRT) has been one of the most important issues in DRAM, since Yaney et al. reported on this phenomenon in 1987. However, the detailed characteristics of VRT have not yet been studied systematically. In this research, VRT phenomenon was investigated systematically by measuring the DC current in test element groups (TEGs) of DRAM and testing the retention time of the DRAM on the chip level . RTS-like fluctuation in Gate Induced Drain Leakage (GIDL) current of Saddle-Fin (S-Fin) type DRAM cell transistor was investigated. Furthermore, two types of fluctuation which have apparently different τhigh (average time duration of high leakage state) to τlow (average time duration of low leakage state) ratio were investigated, and it was found that the energy difference between bistable levels is similar to that of the junction leakage. Traps were generated inside gate oxide in gate-drain overlap region of the recess channel type DRAM cell transistor through Fowler-Nordheim (FN) stress, and GIDL current was observed both in time domain and in frequency domain. It was found that the trap inside gate oxide could generate RTS-like fluctuation in GIDL current. The characteristics of that fluctuation were similar to those of RTS-like fluctuation in GIDL current observed in the non-stressed device. This result shows the possibility that the trap causing VRT in DRAM data retention time can be located inside gate oxide like channel RTS of metal–oxide–semiconductor field-effect transistors (MOSFETs). To study the relationship between the original leakage current fluctuation and the detected VRT from the retention test of DRAM, the real procedure of the VRT measurement of DRAM was simulated. By investigating the results of the simulation, a new effective VRT measurement method was proposed based on the comparison between measurement and simulation. In addition, the characteristics of VRT phenomenon in DRAM was investigated using the VRT characterization method developed in this study. To study trap models related VRT phenomenon in DRAM, we derived equations to calculate the data retention time of DRAM and the activation energy for two trap models, the metastable trap model and oxide trap model. Measuring the data retention time of VRT cells for various bias and temperature conditions, the dependence of activation energy differences in the data retention time on bias at high and low retention states was extracted. Furthermore, the dependence of the electric field on bias at high and low retention states was also extracted. Using those parameters, the two types of trap models were successfully distinguished. Finally, we investigated two types of current, capacitor node dielectric leakage current and operation current of the cell, which can create a RTS -like fluctuation in DRAM. We compared the properties of the capacitor node dielectric leakage current with those of VRT. In addition, we measured the RTS in several different types of cell transistor TEGs. Furthermore, we investigated the characteristics of RTS found in different type of cell transistor TEGs.