Publications
Detailed Information
Reversible Energy Recovery logic circuits and its 8-phase clocked power generator for ultra-low-power applications
Cited 0 time in
Web of Science
Cited 0 time in Scopus
- Authors
- Issue Date
- 1999
- Citation
- IEICE TRANSACTIONS on Electronics, Vol.E82-C, No.4, pp.646-653
- Keywords
- reversible logic ; adiabatic circuit ; clocked power generator ; reversible energy recovery logic (RERL)
- Abstract
- We proposed Reversible Energy Recovery Logic (RERL) using an 8-phase clocking scheme, which is a dual-rail reversible adiabatic logic for ultra-low-energy applications. Because we eliminated non-adiabatic energy loss in RERL by using the concept of reversible logic, RERL has only adiabatic and leakage losses. In this paper we explain its operation and logic design and present its simulation and experimental results. We also present an energy-efficient 8-phase, clocked power generator that uses an off-chip inductor. With simulation results for the full adder, we confirmed that the RERL circuit consumed substantially less energy than other logic circuits at low-speed operation. We evaluated a test chip implemented with a 0.6-µm CMOS technology, which integrated a chain of inverters with a clocked power generator. In the experimental results, the RERL circuit consumed only 4.5% of the dissipated energy of a static CMOS circuit at an optimal operating speed of 40 kHz. In conclusion, RERL is suitable for the applications that do not require high performance but low-energy consumption because its energy consumption can be decreased to the minimum by reducing the operating frequency until adiabatic and leakage losses are equal
- ISSN
- 0916-8516
- Language
- English
- Files in This Item:
Item View & Download Count
Items in S-Space are protected by copyright, with all rights reserved, unless otherwise indicated.