Reversible energy recovery logic circuit without non-adiabatic energy loss

Abstract

The authors propose a reversible energy recovery logic (RERL) circuit for ultra-low-energy consumption, whch consumes only adiabatic energy loss and leakage current loss by completely eliminating non-adiabatic energy loss. It is a dual-rail adiabatic circuit using the concept of reversible logic with a new eight-phase clocking scheme. Simulation results show that at low-speed operation, the RERL consumes much less energy than the complementary static CMOS circuit and other adiabatic logic circuits.