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A mixed-level virtual prototyping environment for SystemC-based design methodology
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Sanggyu | - |
dc.contributor.author | Yoon, Sangyong | - |
dc.contributor.author | Chae, Soo-Ik | - |
dc.date.accessioned | 2009-12-17T05:55:25Z | - |
dc.date.available | 2009-12-17T05:55:25Z | - |
dc.date.issued | 2009 | - |
dc.identifier.citation | Microelectronics Journal. 40(7) 1082-1093. | en |
dc.identifier.issn | 0026-2692 | - |
dc.identifier.uri | https://hdl.handle.net/10371/21264 | - |
dc.description.abstract | Weproposeaflexiblemixed-levelvirtualprototypingenvironment,wheremodelsindifferent
abstraction levelssuchastransactionlevel,register-transferlevel,andsoftwarelevelcanbeco- simulatedtogether.Intheproposedenvironment,thedesignersshouldcaptureatransactionlevel systemmodelbeforehardware–softwarepartitioning,fromwhichmixed-levelvirtualprototyping models canberefinedwithpre-definedandpre-verifiedcommunicationprimitives.Weexplainseveral techniquesemployedintheenvironmentsuchasIDportsforsoftwaretemplateefficiency,abstraction adaptersinSystemCformixedlevelsimulation,andtrace-drivensimulationforfasterperformance evaluation.Moreover,transactionleveldescriptionsinSystemCcanbecompiledandexecutedas softwaretogetherwiththeDEOS,whichisanoperatingsystemthatprovidesSystemCAPIs.We comparedthesimulationspeedofseveralmixed-levelvirtualprototypesofaH.264decodertoshowthe effectiveness oftheproposedenvironment. | en |
dc.language.iso | en | - |
dc.publisher | Elsevier | en |
dc.subject | SystemC | en |
dc.subject | Transactionlevelmodel | en |
dc.subject | Channel | en |
dc.subject | Architecturetemplate | en |
dc.subject | Virtual prototype | en |
dc.title | A mixed-level virtual prototyping environment for SystemC-based design methodology | en |
dc.type | Article | en |
dc.contributor.AlternativeAuthor | 박상규 | - |
dc.contributor.AlternativeAuthor | 윤상용 | - |
dc.contributor.AlternativeAuthor | 채수익 | - |
dc.identifier.doi | 10.1016/j.mejo.2008.05.010 | - |
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