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A cost-effective architecture for HDTV video decoder in ATSC receivers
Cited 5 time in
Web of Science
Cited 10 time in Scopus
- Authors
- Issue Date
- 1998
- Citation
- IEEE Trans. on Consumer Electronics, Vol. 44, No.4, pp.1353-1359
- Abstract
- In this paper, we describe the architecture of an
HDTV video decoder, Vincent5, for MPEG2 MP@HL
video decoding and format conversion of all 18 ATSC
DTV formats in real-time. Vincent5 adopts a dataflow
architecture for its main decoding functions in contrast to
the conventional decoders that use a strict pipelined
structure for them. Consequently, this makes it possible for
us to explore wide design choices in the architecture
decision for each decoding function. In Vincent5 we
introduce a new memory control scheme of reducing the
memory bandwidth, which is necessary in MPEG2
MP@HL decoding for a cost-effective solution. Without
increasing the hardware complexity of VincentS, we embed
three programmable cores into the dedicated hardware to
maximize its programmability. Vincent5 was described
using the VHDL and its functionality was verified with
standard MPEG2 bitstreams. Vincent5 includes 11 5K logic
gates, 118Kb RAM, and 32Kb ROM after logic synthesis
and had been fabricated utilizing 3ML Ohm CMOS
technology.
- ISSN
- 0098-3063
- Language
- English
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