Publications
Detailed Information
Cache Optimization for H.264/AVC Motion Compensation
Cited 0 time in
Web of Science
Cited 0 time in Scopus
- Authors
- Issue Date
- 2008-12
- Citation
- IEICE Trans. Information and Systems, vol. E91-D no. 12 pp.2902-2905
- Keywords
- cache ; H.264 ; motion compensation ; memory bandwidth ; DDR
- Abstract
- In this letter, we propose a cache organization that substantially
reduces the memory bandwidth of motion compensation (MC) in
the H.264/AVC decoders. To reduce duplicated memory accesses to P and
B pictures, we employ a four-way set-associative cache in which its index
bits are composed of horizontal and vertical address bits of the frame buffer
and each line stores an 8 × 2 pixel data in the reference frames. Moreover,
we alleviate the data fragmentation problem by selecting its line size that
equals the minimum access size of the DDR SDRAM. The bandwidth of
the optimized cache averaged over five QCIF IBBP image sequences requires
only 129% of the essential bandwidth of an H.264/AVC MC.
- ISSN
- 0916-8532
- Language
- English
- Files in This Item:
Item View & Download Count
Items in S-Space are protected by copyright, with all rights reserved, unless otherwise indicated.