Performance-driven high-level synthesis with system clock optimization

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Performance-driven high-level synthesis with system clock optimization : 시스템 클록 최적화를 활용한 성능위주의 상위수준합성

DC Field	Value	Language
dc.contributor.advisor	최기영	-
dc.contributor.author	박상헌	-
dc.date.accessioned	2010-01-15T04:18:34Z	-
dc.date.available	2010-01-15T04:18:34Z	-
dc.date.copyright	1999.	-
dc.date.issued	1999	-
dc.identifier.uri	http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000074310	eng
dc.identifier.uri	https://hdl.handle.net/10371/30806	-
dc.description	Thesis (doctoral)--서울대학교 대학원 :전자공학과,1999.	en
dc.format.extent	xiii, 135 p.	en
dc.language.iso	en	en
dc.publisher	서울대학교 대학원	en
dc.subject	상위수준합성	en
dc.subject	high-level synthesis	en
dc.subject	스케쥴링	en
dc.subject	scheduling	en
dc.subject	제어합성	en
dc.subject	control-synthesis	en
dc.subject	시스템클록 최적화	en
dc.subject	bit-level chaining	en
dc.subject	유한상태머신합성	en
dc.subject	system clock optimization	en
dc.title	Performance-driven high-level synthesis with system clock optimization	en
dc.title.alternative	시스템 클록 최적화를 활용한 성능위주의 상위수준합성	-
dc.type	Thesis	-
dc.contributor.department	전자공학과	-
dc.description.degree	Doctor	en

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