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상위단계 합성에서의 타이밍 최적화를 위한 버퍼 삽입 활용 : Utilization of Buffer Insertion for Timing Optimization in High-level Synthesis
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 김태환 | - |
| dc.contributor.author | 박상도 | - |
| dc.date.accessioned | 2010-01-26T06:11:48Z | - |
| dc.date.available | 2010-01-26T06:11:48Z | - |
| dc.date.copyright | 2009. | - |
| dc.date.issued | 2009 | - |
| dc.identifier.uri | http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000038751 | kog |
| dc.identifier.uri | https://hdl.handle.net/10371/44669 | - |
| dc.description | 학위논문(석사) --서울대학교 대학원 :전기. 컴퓨터공학부,2009.8. | ko |
| dc.format.extent | iv, 20장 | ko |
| dc.language.iso | ko | ko |
| dc.publisher | 서울대학교 대학원 | ko |
| dc.subject | 타이밍 | ko |
| dc.subject | Timing | ko |
| dc.subject | 상위 단계 합성 | ko |
| dc.subject | High-Level Synthesis | ko |
| dc.subject | 버퍼 삽입 | ko |
| dc.subject | buffer insertion | ko |
| dc.subject | 설계 흐름 | ko |
| dc.subject | Physical design | ko |
| dc.subject | design flow | ko |
| dc.title | 상위단계 합성에서의 타이밍 최적화를 위한 버퍼 삽입 활용 | ko |
| dc.title.alternative | Utilization of Buffer Insertion for Timing Optimization in High-level Synthesis | ko |
| dc.type | Thesis | - |
| dc.contributor.department | 전기. 컴퓨터공학부 | - |
| dc.description.degree | Master | ko |
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