Browse

전원노이즈 감소를 위한 클락 버퍼의 크기 조절 및 위상 지정 기법
Simultaneous Buffer Sizing and Polarity Assignment for Noise Minimization in Clock Tree Synthesis

Cited 0 time in Web of Science Cited 0 time in Scopus
Authors
장호창
Advisor
김태환
Issue Date
2009
Publisher
서울대학교 대학원
Keywords
클락트리Clock Tree클락버퍼Clock Buffer노이즈Power-Ground Noise
Description
학위논문(석사) --서울대학교 대학원 :전기. 컴퓨터공학부, 2009.2.
Language
Korean
URI
http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000037081

http://hdl.handle.net/10371/44723
Files in This Item:
There are no files associated with this item.
Appears in Collections:
College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Theses (Master's Degree_전기·정보공학부)
  • mendeley

Items in S-Space are protected by copyright, with all rights reserved, unless otherwise indicated.

Browse