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FPGA에서의 성능 최적화 구현을 위한 상위 수준 합성 및 모듈 배치
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- Authors
- Advisor
- 최기영
- Issue Date
- 2004
- Publisher
- 서울대학교 대학원
- Keywords
- 상위 수준 합성 ; high-level synthesis ; 모듈 배치 ; module placement ; 분산 레지스터 구조 ; distributed register architecture ; interconnect delay ; interconnect delay ; multi-cycle ; multi-cycle ; FPGA ; FPGA
- Description
- 학위논문(석사)--서울대학교 대학원 :전기· 컴퓨터공학부,2004.
- Language
- Korean
- URI
- http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000056457
https://hdl.handle.net/10371/48561
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