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Synchronous mirror delay를 이용한 클럭 발생기의 설계 : Design of clock generator using synchronous mirror delay
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- Authors
- Advisor
- 이종덕
- Issue Date
- 2004
- Publisher
- 서울대학교 대학원
- Keywords
- Synchronous mirror delay ; Synchronous mirror delay ; Double data rate ; Double data rate ; Delay locked loop ; Delay locked loop ; Clock recovery circuit ; Clock recovery circuit ; 다중 위상 동기 ; Multi-phase locking ; 동기 메모리 ; Sync memory ; 동기 오차 ; Synchronizing error ; Jitter ; Jitter
- Description
- 학위논문(박사)--서울대학교 대학원 :전기공학부,2004.
- Language
- Korean
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