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SOI MEMS 공정의 면적 최소화를 위한 웨이퍼수준 밀봉 실장 기술 : Wafer-level hermetic packaging technology for area minimization in SOI MEMS process
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- Authors
- Advisor
- 조동일
- Issue Date
- 2007
- Publisher
- 서울大學校 大學院
- Keywords
- 미세전기기계시스템 ; MEMS ; 멤즈 ; wafer-level hermetic packaging ; 통전로 ; electrical feed through ; 웨이퍼수준 ; 밀봉 ; 실장
- Description
- 學位論文(博士)--서울大學校 大學院 :電氣·컴퓨터工學部,2007.
- Language
- Korean
- URI
- http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000045162
https://hdl.handle.net/10371/48938
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