VLSI Implementation of a Soft Bit-Flipping Decoder for PG-LDPC Codes

Abstract

Low-density parity-check codes are known to show higher error correcting performance than conventional algebraic codes. However, the VLSI implementation of the codes has been considered very difficult especially when the row or column weight of them is high. In this paper, a projective-geometry(PG) LDPC code is implemented in VLSI employing the proposed soft bit flipping(SBF) algorithm. In addition to the processing unit sharing, the pipelining technique is employed to increase the decoding throughput. With the (1057, 813) PG-LDPC code, the implemented 4-bit SBF decoder consumes only a small area of 2.5mm^2, while providing the throughput of 6.5Gbps and good error performance close to the floating-point sumproduct algorithm(SPA) by 0.6dB at the frame error rate(FER) of 10^(-4).