SHERP

Packing Buffer for Efficient Irregular Data access in SIMD Processors

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Authors
Chang, Hoseok; Lim, Jieun; Sung, Wonyong
Issue Date
2009
Citation
제16회 한국반도체학술대회
Abstract
The performance of an SIMD (Single Instruction Multiple Data) processor is bounded by the memory bottleneck; most of which is due to the overhead for preparing aligned vector data. In this paper, we have added a hardware unit to an SIMD processor to reduce the alignment overhead. The proposed packing buffer contains a small size multi-port memory block for which multiple addresses are generated by using a vector index register. Since the packing buffer has a small size, it requires neither complex hardware nor increased CPU cycle time. DSP benchmarks are used to measure the performance efficiency.
Language
Korean
URI
http://kcs.cosar.or.kr

http://hdl.handle.net/10371/6141
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Others_전기·정보공학부
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