SHERP

낸드 플래시 메모리 오류 정정을 위한 병렬 BCH 복호기의 최적 설계

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Authors
최효진; 지현우; 성원용
Issue Date
2009
Citation
제16회 한국반도체학술대회
Abstract
In this work, we have developed a parallel BCH decoder for multi-level cell NAND flash memory. The decoder is designed to require minimum chip area as well as minimum power consumption for NAND flash memory applications. To achieve this goal, the parallle factor of each functional block is determined by using design exploitation techniques.
Language
Korean
URI
http://kcs.cosar.or.kr

http://hdl.handle.net/10371/6149
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Others_전기·정보공학부
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