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낸드 플래시 메모리 오류 정정을 위한 병렬 BCH 복호기의 최적 설계
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 최효진 | - |
| dc.contributor.author | 지현우 | - |
| dc.contributor.author | 성원용 | - |
| dc.date.accessioned | 2009-08-05T03:23:28Z | - |
| dc.date.available | 2009-08-05T03:23:28Z | - |
| dc.date.issued | 2009 | - |
| dc.identifier.citation | 제16회 한국반도체학술대회 | en |
| dc.identifier.uri | http://kcs.cosar.or.kr | - |
| dc.identifier.uri | https://hdl.handle.net/10371/6149 | - |
| dc.description.abstract | In this work, we have developed a parallel BCH decoder for multi-level cell NAND flash memory. The decoder is designed to require minimum chip area as well as minimum power consumption for NAND flash memory applications. To achieve this goal, the parallle factor of each functional block is determined by using design exploitation techniques. | en |
| dc.description.sponsorship | 본 논문은 지식경제부 출연금으로 ETRI, 시스템반도체
산업진흥센터에서 수행한 IT SoC 핵심설계인력양성사업의 연구결과입니다. | en |
| dc.language.iso | ko | en |
| dc.title | 낸드 플래시 메모리 오류 정정을 위한 병렬 BCH 복호기의 최적 설계 | en |
| dc.type | Conference Paper | en |
| dc.contributor.AlternativeAuthor | Choi, Hyojin | - |
| dc.contributor.AlternativeAuthor | Ji, Hyunwoo | - |
| dc.contributor.AlternativeAuthor | Sung, Wonyong | - |
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