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Multimedia processor-based implementation of an error-diffusion halftoning algorithm exploiting subword parallelism

Cited 12 time in Web of Science Cited 17 time in Scopus
Authors
Ahn, Jae-Woo; Sung, Wonyong
Issue Date
2001-02
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
IEEE Trans. Circuits and Systems for Video Technology, vol. 11, no. 2, pp. 129-138, Feb. 2001
Keywords
Error-diffusion halftoning algorithmmultimedia processorPentium MMXsubword parallelism
Abstract
Multimedia processor-based implementation of
digital image processing algorithms has become important
since several multimedia processors, such as the Intel Pentium
MMX, are now available and can replace special-purpose hardware-
based systems because of their flexibility. Multimedia
processors increase throughput by processing multiple pixels
simultaneously using a subword-parallel arithmetic and logic unit
architecture. The error-diffusion halftoning algorithm employs
feedback of quantized output signals to faithfully convert a
multi-level image to a binary image or to one with fewer levels
of quantization. This makes it difficult to achieve speedup by
utilizing the multimedia extension. In this study, the error-diffusion
halftoning algorithm is implemented for a multimedia
processor using three methods: single-pixel, single-line, and
multiple-line processing. The single-pixel approach is the closest
to conventional implementations, but the multimedia extension is
used only in the filter kernel. The single-line approach computes
multiple pixels in one scan-line simultaneously, but requires
a complex algorithm transformation to remove dependencies
between pixels. The multiple-line method exploits parallelism
by employing a skewed data structure and processing multiple
pixels in different scan-lines. The Pentium MMX instruction set is
used for quantitative performance evaluation including run-time
overheads and misaligned memory accesses. A speedup of more
than ten times is achieved compared to the software (integer C)
implementation on a conventional processor for the structurally
sequential error-diffusion halftoning algorithm.
ISSN
1051-8215
Language
English
URI
http://hdl.handle.net/10371/6153
DOI
https://doi.org/10.1109/76.905980
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Journal Papers (저널논문_전기·정보공학부)
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