SHERP

PG-LDPC 부호를 위한 Soft Bit-Flipping 복호기의 파이프라인 구현
Pipelined Implementation of Soft Bit-Flipping Decoders for PG-LDPC codes

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Authors
김종홍; 조준호; 지현우; 성원용
Issue Date
2009-07
Citation
2009 대한전자공학회 하계종합학술대회
Abstract
Low-density parity-check codes are known to show higher error correcting performance than conventional algebraic codes. However, it is hard to implement in hardware when the row or column weight of them is high. In this paper, we implemented a VLSI for projective-geometry(PG) LDPC codes employing the soft bit-flipping(SBF) algorithm which has low computational and interconnection complexities. In addition to the parallel architecture, the pipelining technique and the processing unit sharing technique are employed to increase the throughput and reduce the chip area. The implemented (1057,813) 4-bit SBF decoder consumes a small area of 2.7mm2, while providing the throughput of 11.3Gbps.
Language
Korean
URI
http://hdl.handle.net/10371/6156

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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Others_전기·정보공학부
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