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Algorithm and software optimization of variable block size motion estimation for H.264/AVC on a VLIW–SIMD DSP
Cited 2 time in
Web of Science
Cited 3 time in Scopus
- Authors
- Issue Date
- 2008-01-10
- Publisher
- Springer Verlag
- Citation
- J Sign Process Syst, 51(3), 289-302, Jun.
- Keywords
- variable block size motion estimation ; H.264/AVC encoder ; VLIW (very long instruction word) ; SIMD (single instruction multiple data)
- Abstract
- We implemented the H.264/AVC variable block
size motion estimation (VBSME) using a very long
instruction word (VLIW)–single instruction multiple data
(SIMD) digital signal processor (DSP). The SAD_Reuse
method which has a regular structure is chosen for VBSME
not only to remove redundant sum of absolute difference
(SAD) operations but also to utilize the instruction level
parallelism (ILP) and data level parallelism (DLP) of the
architecture. A fast mode decision algorithm is developed
to reduce the number of compare and update operations
and simplify the rate distortion optimization (RDO). The
developed fast mode decision uses the difference of motion
vectors and the maximum a posteriori (MAP) estimation of
the rate-distortion costs. Several advanced software techniques
that include software pipelining and packed-data
processing are employed. Especially, memory access
overhead reduction schemes including the multi-block
processing and the inter-procedural scheduling are used
for the software optimization. In order to reduce the write
buffer full in the quarter pixel ME, a 4 bit quantization
scheme is developed, which increases the number of
arithmetic operations but decreases the stall cycles very
much. The implemented variable block size ME for H.264/
AVC requires an average of 9 M and 78 Mcycles per frame
for QCIF and CIF size video sequences, respectively, in the
TMS320C64x DSP architecture.
- ISSN
- 1939-8018 (print)
1939-8115 (online)
- Language
- English
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