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An 8 x 8 nRERL serial multiplier for ultra-low-power applications
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lim, Joonho | - |
dc.contributor.author | Kim, Donggyu | - |
dc.contributor.author | Kang, Sangcheol | - |
dc.contributor.author | Chae, Soo-Ik | - |
dc.date.accessioned | 2010-04-01T01:07:09Z | - |
dc.date.available | 2010-04-01T01:07:09Z | - |
dc.date.issued | 2000-01 | - |
dc.identifier.citation | Proc. of ASP-DAC'98, pp.35-36 | en |
dc.identifier.isbn | 0780359747 | - |
dc.identifier.uri | https://hdl.handle.net/10371/62268 | - |
dc.description.abstract | An 8 x 8-b nRERL serial multiplier is
implemented in a 0.6- m n-well 3-metal CMOS pro- cess. nRERL (nMOS Reversible Energy Recov ery Logic) is a new reversible adiabatic logic circuit, which can be operated at the leakage-current lev el for ultra- low-energy applications. Measurement results show ed that the nRERL serial multiplier consumed only 0.9 % of the energy dissipation of the static CMOS one at the operating frequency 100 kHz at 5V, where its adiabatic and leakage losses were about equal. | en |
dc.description.sponsorship | The test chip was fabricated with the help of IDEC
program of KAIST, Taejon, Korea. This paper was sup- ported by NON DIRECTED RESEARCH FUND, Korea Research Foundation,throught Inter-university Semicon- ductor Research Center, Seoul National University, Seoul, Korea, from 1996 to 1999. | en |
dc.language.iso | en | en |
dc.publisher | IEEE | en |
dc.title | An 8 x 8 nRERL serial multiplier for ultra-low-power applications | en |
dc.type | Conference Paper | en |
dc.contributor.AlternativeAuthor | 임준호 | - |
dc.contributor.AlternativeAuthor | 김동규 | - |
dc.contributor.AlternativeAuthor | 강상철 | - |
dc.contributor.AlternativeAuthor | 채수익 | - |
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