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An Optimized Rendering Algorithm for Hardware Implementation of OpenVG 2D Vector Graphics
IEEE

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Authors
Cha, Kilhyung; Kim, Daewoong; Chae, Soo-Ik
Issue Date
2008-11
Citation
International SoC Design Conference, Vol.1 ORAL Session pp.338-341
Keywords
OpenVG2D Vector Graphics Hardware Accelerator
Abstract
An optimized rendering algorithm of the OpenVG 2D
vector graphics for hardware implementation is presented in this
paper. In the rendering algorithm we adopted a hybrid of raster
and vector rendering, which uses vector rendering only within
each scanline, to reduce both the number of external memory
accesses and the computational complexity. We implemented a
hardware accelerator with the proposed algorithm. Experimental
results show that our hardware accelerator can handle 11.8 fps of
Tiger image for a QVGA panel at the operating clock frequency
of 100 MHz.
Language
English
URI
http://hdl.handle.net/10371/62279
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Others_전기·정보공학부
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