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An Optimized Rendering Algorithm for Hardware Implementation of OpenVG 2D Vector Graphics : IEEE
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Cha, Kilhyung | - |
dc.contributor.author | Kim, Daewoong | - |
dc.contributor.author | Chae, Soo-Ik | - |
dc.date.accessioned | 2010-04-01T01:26:02Z | - |
dc.date.available | 2010-04-01T01:26:02Z | - |
dc.date.issued | 2008-11 | - |
dc.identifier.citation | International SoC Design Conference, Vol.1 ORAL Session pp.338-341 | en |
dc.identifier.isbn | 9781424425990 | - |
dc.identifier.uri | https://hdl.handle.net/10371/62279 | - |
dc.description.abstract | An optimized rendering algorithm of the OpenVG 2D
vector graphics for hardware implementation is presented in this paper. In the rendering algorithm we adopted a hybrid of raster and vector rendering, which uses vector rendering only within each scanline, to reduce both the number of external memory accesses and the computational complexity. We implemented a hardware accelerator with the proposed algorithm. Experimental results show that our hardware accelerator can handle 11.8 fps of Tiger image for a QVGA panel at the operating clock frequency of 100 MHz. | en |
dc.language.iso | en | en |
dc.subject | OpenVG | en |
dc.subject | 2D Vector Graphics Hardware Accelerator | en |
dc.title | An Optimized Rendering Algorithm for Hardware Implementation of OpenVG 2D Vector Graphics | en |
dc.title.alternative | IEEE | en |
dc.type | Conference Paper | en |
dc.contributor.AlternativeAuthor | 차길형 | - |
dc.contributor.AlternativeAuthor | 김대웅 | - |
dc.contributor.AlternativeAuthor | 채수익 | - |
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