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Complexity reduction in an nRERL microprocessor

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Authors
Kim, Seokkee; Chae, Soo-Ik
Issue Date
2005-08
Publisher
ACM (Association for Computing Machinery )
Citation
International Symposium on Low Power Electronics and Design, pp.180-185
Keywords
MicroprocessornMOS Reversible Energy Recovery Logic(nRERL)Clocked Power Generator (CPG)Complexity ReductionBuffer skippingReversibility Breaking
Abstract
We describe an adiabatic microprocessor implemented with a
reversible logic, nRERL [1]. We employed an 8-phase clocked
power instead of 6-phase one to reduce the number of buffers
required for the phase aligning in the adiabatic microprocessor.
Furthermore, by breaking the logic reversibility with self-energy
recovery circuits, we also reduced its complexity as well as its
energy consumption.
We integrated an 8-bit nRERL microprocessor with an 8-phase
clocked power generator into a chip with 0.25μm CMOS
technology. Its minimum energy consumption of 4.67μA/MHz
was measured at Vdd=2.4V and f=651kHz, which was about 40%
compared to the previous 6-phase version. Its circuit complexity
was also reduced down to 65% that of its 6-phase version.
Language
English
URI
http://hdl.handle.net/10371/62283
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Others_전기·정보공학부
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