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Complexity reduction in an nRERL microprocessor
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Seokkee | - |
dc.contributor.author | Chae, Soo-Ik | - |
dc.date.accessioned | 2010-04-01T01:32:17Z | - |
dc.date.available | 2010-04-01T01:32:17Z | - |
dc.date.issued | 2005-08 | - |
dc.identifier.citation | International Symposium on Low Power Electronics and Design, pp.180-185 | en |
dc.identifier.isbn | 1595931376 | - |
dc.identifier.uri | https://hdl.handle.net/10371/62283 | - |
dc.description.abstract | We describe an adiabatic microprocessor implemented with a
reversible logic, nRERL [1]. We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers required for the phase aligning in the adiabatic microprocessor. Furthermore, by breaking the logic reversibility with self-energy recovery circuits, we also reduced its complexity as well as its energy consumption. We integrated an 8-bit nRERL microprocessor with an 8-phase clocked power generator into a chip with 0.25μm CMOS technology. Its minimum energy consumption of 4.67μA/MHz was measured at Vdd=2.4V and f=651kHz, which was about 40% compared to the previous 6-phase version. Its circuit complexity was also reduced down to 65% that of its 6-phase version. | en |
dc.language.iso | en | en |
dc.publisher | ACM (Association for Computing Machinery ) | en |
dc.subject | Microprocessor | en |
dc.subject | nMOS Reversible Energy Recovery Logic(nRERL) | en |
dc.subject | Clocked Power Generator (CPG) | en |
dc.subject | Complexity Reduction | en |
dc.subject | Buffer skipping | en |
dc.subject | Reversibility Breaking | en |
dc.title | Complexity reduction in an nRERL microprocessor | en |
dc.type | Conference Paper | en |
dc.contributor.AlternativeAuthor | 김석기 | - |
dc.contributor.AlternativeAuthor | 채수익 | - |
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