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High performance IPC hardware accelerator and communication network for MPSoCs
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Koo, Moonmo | - |
dc.contributor.author | Chae, Soo-Ik | - |
dc.date.accessioned | 2010-04-01T01:50:59Z | - |
dc.date.available | 2010-04-01T01:50:59Z | - |
dc.date.issued | 2008-11 | - |
dc.identifier.citation | International SoC Design Conference, Vol.3 CDC Session pp.21-22 | en |
dc.identifier.uri | https://hdl.handle.net/10371/62292 | - |
dc.description.abstract | In this paper, we explain a configurable IPC module
for multimedia MPSoCs, which was implemented in a MPW chip that include three ARM7 CPU cores. According to the test results for an M-JPEG and a H.264 decoder, its IPC synchronization overheads are not more than 1% when the synchronization period is about 5000 cycles. | en |
dc.description.sponsorship | This work was supported by the IC Design Education
Center (IDEC) in KAIST, and the Seoul R&BD Program. | en |
dc.language.iso | en | en |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en |
dc.subject | MPSoC | en |
dc.subject | IPC | en |
dc.subject | synchronization | en |
dc.subject | multimedia | en |
dc.subject | H.264 | en |
dc.title | High performance IPC hardware accelerator and communication network for MPSoCs | en |
dc.type | Conference Paper | en |
dc.contributor.AlternativeAuthor | 구문모 | - |
dc.contributor.AlternativeAuthor | 채수익 | - |
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