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High performance IPC hardware accelerator and communication network for MPSoCs

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dc.contributor.authorKoo, Moonmo-
dc.contributor.authorChae, Soo-Ik-
dc.date.accessioned2010-04-01T01:50:59Z-
dc.date.available2010-04-01T01:50:59Z-
dc.date.issued2008-11-
dc.identifier.citationInternational SoC Design Conference, Vol.3 CDC Session pp.21-22en
dc.identifier.urihttps://hdl.handle.net/10371/62292-
dc.description.abstractIn this paper, we explain a configurable IPC module
for multimedia MPSoCs, which was implemented in a MPW chip
that include three ARM7 CPU cores. According to the test results
for an M-JPEG and a H.264 decoder, its IPC synchronization
overheads are not more than 1% when the synchronization
period is about 5000 cycles.
en
dc.description.sponsorshipThis work was supported by the IC Design Education
Center (IDEC) in KAIST, and the Seoul R&BD Program.
en
dc.language.isoenen
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en
dc.subjectMPSoCen
dc.subjectIPCen
dc.subjectsynchronizationen
dc.subjectmultimediaen
dc.subjectH.264en
dc.titleHigh performance IPC hardware accelerator and communication network for MPSoCsen
dc.typeConference Paperen
dc.contributor.AlternativeAuthor구문모-
dc.contributor.AlternativeAuthor채수익-
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