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지연시간 편차를 고려한 클락 버퍼 위상 지정 기법 : Clock Buffer Polarity Assignment Considering the Effect of Delay Variations
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- Authors
- Advisor
- 김태환
- Issue Date
- 2010
- Publisher
- 서울대학교 대학원
- Keywords
- 클락 트리 ; clock tree ; 시간 편차 ; timing variation ; 전원 노이즈 ; power ; 회로 최적화 ; ground noise ; optimization circuits
- Description
- 학위논문(석사) --서울대학교 대학원 :전기. 컴퓨터공학부,2010.2.
- Language
- Korean
- URI
- http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000033417
https://hdl.handle.net/10371/65223
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