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High-resolution time-to-digital converter utilising fractional difference conversion scheme
Cited 9 time in
Web of Science
Cited 11 time in Scopus
- Authors
- Issue Date
- 2010-03-18
- Citation
- Electronics Letters- IEE (2010),46(6):398
- Keywords
- digital converter ; High-resolution
- Abstract
- A high-resolution process, voltage and temperature (PVT)-insensitive
time-to-digital converter (TDC) is presented, based on a Vernier
delay-line, in which the propagation delays in the upper and lower
buffer chains are stabilised by two different delay-locked-loops
(DLLs). The limitation on its resolution, imposed by DLL jitter and
input range of time intervals, is analysed. Simulation results show
that the proposed TDC achieves a resolution as high as 22.7 ps while
consuming only 2.7 mW.
- ISSN
- 0013-5194
- Language
- English
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