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A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs

Cited 44 time in Web of Science Cited 66 time in Scopus
Authors

Kim, Suhwan; Stephen V., Kosonocky; Daniel R, Knebel; Kevin, Stawiasz; Marios C, Papaefthymiou

Issue Date
2007-07
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
IEEE Transactions on Circuits and Systems Part 2 Express Briefs, vol. 54, no. 7, pp. 586-590
Keywords
Deep-submicrometer CMOSground bounce noiselow voltagemulti-threshold CMOS (MTCMOS)
Abstract
Most existing power gating structures provide only
one power-saving mode. We propose a novel power gating structure
that supports both a cutoff mode and an intermediate powersaving
and data-retaining mode. Experiments with test structures
fabricated in 0.13- mCMOSbulk technology showthat our power
gating structure yields an expanded design space with more powerperformance
tradeoff alternatives.
ISSN
1549-7747
Language
English
URI
https://hdl.handle.net/10371/68015
DOI
https://doi.org/10.1109/TCSII.2007.894428
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