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Parallel Scalability in Speech Recognition
DC Field | Value | Language |
---|---|---|
dc.contributor.author | You, Kisun | - |
dc.contributor.author | Chong, Jike | - |
dc.contributor.author | Yi, Youngmin | - |
dc.contributor.author | Gonina, Ekaterina | - |
dc.contributor.author | Christopher.J., Hughes | - |
dc.contributor.author | Chen, Yen-Kuang | - |
dc.contributor.author | Sung, Wonyong | - |
dc.contributor.author | K., Keutzer | - |
dc.date.accessioned | 2010-07-23 | - |
dc.date.available | 2010-07-23 | - |
dc.date.issued | 2009-11 | - |
dc.identifier.citation | IEEE Signal Processing Magazine, vol. 25, no. 6, pp. 124-135 | en |
dc.identifier.issn | 1053-5888 | - |
dc.identifier.uri | https://hdl.handle.net/10371/68656 | - |
dc.description.abstract | We propose four application-level implementation alternatives called algorithm styles and construct highly optimized implementations on two parallel platforms: an Intel Core i7 multicore processor and a NVIDIA GTX280 manycore processor. The highest performing algorithm style varies with the implementation platform. On a 44-min speech data set, we demonstrate substantial speedups of 3.4 X on Core i7 and 10.5 X on GTX280 compared to a highly optimized sequential implementation on Core i7 without sacrificing accuracy. The parallel implementations contain less than 2.5% sequential overhead, promising scalability and significant potential for further speedup on future platforms. | en |
dc.language.iso | en | en |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en |
dc.title | Parallel Scalability in Speech Recognition | en |
dc.type | Article | en |
dc.contributor.AlternativeAuthor | 유기선 | - |
dc.contributor.AlternativeAuthor | 이영민 | - |
dc.contributor.AlternativeAuthor | 성원용 | - |
dc.identifier.doi | 10.1109/MSP.2009.934124 | - |
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