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Schedule-Aware Performance Estimation of Communication Architecture for Efficient Design Space Exploration
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Sungchan | - |
dc.contributor.author | Im, Chaeseok | - |
dc.contributor.author | Ha, Soonhoi | - |
dc.date.accessioned | 2009-08-21T04:18:56Z | - |
dc.date.available | 2009-08-21T04:18:56Z | - |
dc.date.issued | 2005-05 | - |
dc.identifier.citation | IEEE Trans.Very Large Scale Integration systems, vol. 13, pp. 539-552, May. 2005 | en |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://hdl.handle.net/10371/7438 | - |
dc.description.abstract | In this paper,we are concerned about performance estimation
of bus-based communication architectures assuming that task partitioning and scheduling on processing elements are already determined. Since communication overhead is dynamic and unpredictable due to bus contention, a simulation-based approach seems inevitable for accurate performance estimation. However, it is too time-consuming to be used for exploring the wide design space of bus architectures. We propose a static performance-estimation technique based on a queueing analysis assuming that the memory traces and the task schedule information are given. We use this static estimation technique as the first step in our design space exploration framework to prune the design space drastically before applying a simulation-based approach to the reduced design space. Experimental results show that the proposed technique is several orders of magnitude faster than a trace-driven simulation while keeping the estimation error within 10% consistently in various communication architecture configurations. | en |
dc.description.sponsorship | This work was supported by the National Research Laboratory under Program
M1-0104-00-0015, Brain Korea 21 Project, and the IT-SoC project. ICT at Seoul National University provided research facilities for this study. | en |
dc.language.iso | en | en |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en |
dc.subject | Communication architecture | en |
dc.subject | design space exploration | en |
dc.subject | performance estimation | en |
dc.subject | queueing theory | en |
dc.title | Schedule-Aware Performance Estimation of Communication Architecture for Efficient Design Space Exploration | en |
dc.type | Article | en |
dc.contributor.AlternativeAuthor | 김성찬 | - |
dc.contributor.AlternativeAuthor | 임채석 | - |
dc.contributor.AlternativeAuthor | 하순회 | - |
dc.identifier.doi | 10.1109/TVLSI.2004.842912 | - |
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