SHERP

Efficient Exploration of Bus-Based System-on-Chip Architectures

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Authors
Kim, Sungchan; Ha, Soonhoi
Issue Date
2006-07
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
IEEE Trans.Very Large Scale Integration systems, vol. 14, pp. 681-692, July 2006
Keywords
Communication architecturedesign space explorationmemory allocationmultitaskperformance estimation
Abstract
Separation between computation and communication
in system design allows system designers to explore the communication
architecture independently after component selection and
mapping decision is made. In this paper, we present an iterative
two-step exploration methodology for bus-based on-chip communication
architecture for multitask applications. We assume that
the memory traces from the processing components are given.
The proposed methodology uses a static performance estimation
technique extended for multitask applications to reduce the design
space quickly and drastically and applies a trace-driven simulation
to the reduced set of design candidates for accurate performance
estimation. For the case that local memory traffics as well as
shared memory traffics are involved in bus contention, memory
allocation is considered as an important axis of the design space
in our technique. Experimental results show that the proposed
methodology achieves significant performance gain by optimizing
on-chip communication only, up to almost 100% compared with
an initial single shared bus architecture, in both two real-life
examples, a four-Channel digital video recorder and an equalizer
for OFDM DVB-T receiver
ISSN
1063-8210
Language
English
URI
http://hdl.handle.net/10371/7439
DOI
https://doi.org/10.1109/TVLSI.2006.878260
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Computer Science and Engineering (컴퓨터공학부)Journal Papers (저널논문_컴퓨터공학부)
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