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An InGaAs/InP p-i-n-JFET OEIC with a wing-shaped p+-InP layer

DC Field Value Language
dc.contributor.authorPark, Ki Sung-
dc.contributor.authorOh, Kwang Ryong-
dc.contributor.authorKim, Jeong Soo-
dc.contributor.authorLee, Yong Tag-
dc.contributor.authorKim, Sung June-
dc.contributor.authorKwon, Young Se-
dc.date.accessioned2009-09-07T23:55:47Z-
dc.date.available2009-09-07T23:55:47Z-
dc.date.issued1992-04-
dc.identifier.citationIEEE Photon. Technol. Lett., vol. 4, pp. 387-389, April 1992en
dc.identifier.issn1041-1135-
dc.identifier.urihttp://hdl.handle.net/10371/8871-
dc.description.abstractA new receiver OEIC structure with an InGaAs
p-i-n photodiode, InGaAs self-aligned junction FET’s and a
bias resistor has been fabricated on a semi-insulating InP substrate.
The fabrication processes are highly compatible between
the photodiode and the JFET, and reduction in FET gate length
is achieved using anisotropic selective etching and a two-step
OMVPE growth schedule.
The 80 pm diameter p-i-n detector exhibits a leakage current
of 2 nA and a capacitance of about 0.35 pF at -5 V bias
voltage. Extrinsic transconductance and a gate-source capacitance
of the JFET are typically 45 mS/mm and 4.0 pF/mm at
OV, respectively. The maximum voltage gain of the pre-amplifier
is 12.5 and the bandwidth of the p-i-n amplifier OEIC is expected
to be about 1.2 GHz.
en
dc.language.isoen-
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en
dc.titleAn InGaAs/InP p-i-n-JFET OEIC with a wing-shaped p+-InP layeren
dc.typeArticleen
dc.contributor.AlternativeAuthor박기성-
dc.contributor.AlternativeAuthor오광룡-
dc.contributor.AlternativeAuthor김정수-
dc.contributor.AlternativeAuthor이용택-
dc.contributor.AlternativeAuthor김성준-
dc.contributor.AlternativeAuthor권용세-
dc.identifier.doi10.1109/68.127223-
Appears in Collections:
College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Journal Papers (저널논문_전기·정보공학부)
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