S-Space College of Engineering/Engineering Practice School (공과대학/대학원) Dept. of Electrical and Computer Engineering (전기·정보공학부) Journal Papers (저널논문_전기·정보공학부)
A low-power high-speed ion-implanted JFET for InP-based monolithic optoelectronic IC's
- Kim, Sung June; Wang, K.; Vella-Coleiro, G.; Lutze, J.; Ota, Y.; Guth, G.
- Issue Date
- IEEE Electron Device Lett., vol. 8, pp. 518-520, Nov. 1987
- We describe a high-performance fully ion-implanted planar
InP junction FET fabricated by a shallow (4000-A) n-channel implant,
an n+ source-drain implant to reduce FET series resistance, and a p-gate
implant to form a shallow (2000-A) abrupt p-n junction, followed by a
rapid thermal activation. From FET’s with gates 2 pm long, a transconductance
of 50 mS/mm and an output impedance of 400 O.mm are
measured at zero gate bias with a gate capacitance of 1.2 pF/mm. The
FET has a threshold voltage of - 2.4 V, and a saturated drain current of
60 mA/mm at V,, = 0 V with negligible drift.
- Files in This Item: