A low-power high-speed ion-implanted JFET for InP-based monolithic optoelectronic IC's

Abstract

We describe a high-performance fully ion-implanted planar InP junction FET fabricated by a shallow (4000-A) n-channel implant, an n+ source-drain implant to reduce FET series resistance, and a p-gate implant to form a shallow (2000-A) abrupt p-n junction, followed by a rapid thermal activation. From FETs with gates 2 pm long, a transconductance of 50 mS/mm and an output impedance of 400 O.mm are measured at zero gate bias with a gate capacitance of 1.2 pF/mm. The FET has a threshold voltage of - 2.4 V, and a saturated drain current of 60 mA/mm at V,, = 0 V with negligible drift.