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CMOS compatibility of a micromachining process developed for semiconductor neural probe

DC Field Value Language
dc.contributor.authorAn, S.K.-
dc.contributor.authorOh, S.J.-
dc.contributor.authorKim, Sung June-
dc.date.accessioned2009-09-08T03:27:44Z-
dc.date.available2009-09-08T03:27:44Z-
dc.date.issued2001-10-25-
dc.identifier.citationProceedings of the 23rd Annual International Conference of the IEEE Engeering in Medicine and Biology Society, vol. 4, pp. 3443-3445, Istanbul, Turkey, October 25-28, 2001en
dc.identifier.isbn0-7803-7211-5-
dc.identifier.issn1094-687X-
dc.identifier.urihttp://hdl.handle.net/10371/8904-
dc.description.abstractNeural probes are made on silicon substrate using a micromachining process with low temperature steps only. A deep silicon etch ("Bosch") process was used for the probe shaping. CMOS compatibility of the process was checked and reported in this paper. Test transistor patterns generated using standard CMOS fabrication line were exposed to a post-CMOS probe making process including dielectric deposition, gold metalization and the dry etching step, while changes of test transistor characteristics were monitored. Threshold voltage was found virtually unchanged for both nand p-type MOS transistors. When excess plasma exposure was done, however, non-trivial shift in p-MOS threshold was observed.en
dc.language.isoen-
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en
dc.subjectNeural probesen
dc.subjectCMOS compatibilityen
dc.titleCMOS compatibility of a micromachining process developed for semiconductor neural probeen
dc.typeConference Paperen
dc.contributor.AlternativeAuthor김성준-
Appears in Collections:
College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Others_전기·정보공학부
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