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Effect of Substrate Bias on Deposition Behavior of Charged Silicon Nanoparticles in ICP-CVD Process : 유도결합플라즈마를 이용한 화학기상증착 공정 중에 생성되는 하전된 실리콘 나노 입자의 증착 거동에 대한 기판 바이어스 효과

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dc.contributor.advisor황농문-
dc.contributor.author유승완-
dc.date.accessioned2017-07-13T05:53:17Z-
dc.date.available2017-07-13T05:53:17Z-
dc.date.issued2016-08-
dc.identifier.other000000137150-
dc.identifier.urihttps://hdl.handle.net/10371/118098-
dc.description학위논문 (박사)-- 서울대학교 대학원 : 재료공학부, 2016. 8. 황농문.-
dc.description.abstractThe effect of a substrate bias on the deposition behavior of crystalline silicon nanoparticles during inductively coupled plasma chemical vapor deposition (ICP-CVD) was approached by nonclassical crystallization, in which the building block is a nanoparticle rather than an individual atom or molecule. This study consists of two major parts. One is the effect of the substrate bias on the deposition behavior of crystalline silicon nanoparticles during the thin-film deposition condition in the ICP-CVD process. The other is the effect of the substrate bias on the deposition behavior of crystalline silicon nanoparticles during the nanoparticle synthesis condition in the ICP-CVD process
In the first part, the coexistence of positively and negatively charged nanoparticles in the plasma and their role in Si film deposition are confirmed by applying a bias voltage on the substrate, which is so small as not to vary the plasma potential. The sizes of positively and negatively charged nanoparticles captured on the TEM grid membrane were respectively 2.7 ~ 5.5 nm and 6 ~ 13 nm. The film deposited by positively charged nanoparticles has a typical columnar structure. In contrast, the film deposited by negatively charged nanoparticles has the structure like a powder compact with the deposition rate about three times higher than that deposited by positively charged nanoparticles. All the films have crystallinity although the substrate is at room temperature, which is attributed to the deposition of crystalline nanoparticles formed in the plasma. The film deposited by negatively charged nanoparticles has the highest crystalline fraction of 0.84.
In the second part, the effect of the substrate bias on the size and amount of crystalline silicon nanoparticles deposited on the substrate with inserting grounded grids are investigated in an inductively coupled plasma chemical vapor deposition (ICP-CVD) process. By inserting grounded grids above the substrate, the lower region of the grounded grids was separated from the plasma. Thereby, the film formation in the ICP-CVD process could be avoided on the substrate and as a result crystalline Si nanoparticles formed in the plasma could be deposited on the substrate. Moreover the size and the amount of nanoparticles could be controlled by applying the direct current (DC) bias on the substrate. When the 1 mm square mesh grid was used, the nanoparticle flux was increased as the negative substrate bias was increased from 0 V to - 50 V. On the other hand, when positive biases were applied to the substrate, Si nanoparticles were not deposited at all. When the 2 mm square mesh grid was used, sizes of nanoparticles were increased as the substrate bias was increased from -50 V to 50 V.
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dc.description.tableofcontentsChapter 1. Introduction 1
1.1. Theory of Charged Nanoparticles 1
1.1.1 Introduction to Non-classical crystallization 1
1.1.2 Charged Nanoparticles in Diamond CVD 3


Chapter 2. Effect of Substrate Bias on Deposition Behavior of Charged Silicon Nanoparticle in ICP-CVD Process 9
2.1 Introduction 9
2.2 Experiments 12
2.3 Results and Discussion 15
2.4 Conclusions 26

Chapter 3. Application of Charged Nanoparticles Theory in ICP-CVD process: Enhancement of Generation of Positively Charged Nanoparticles 28
3.1 Introduction 28
3.2 Experiments 29
3.3 Results and Discussion 31
3.4 Conclusions 36

Chapter 4. Control of Nanoparticle Size and Their Amount by Using the Mesh Grid and the DC-Biased Substrate in Silane ICP-CVD Process 37
4.1 Introduction 37
4.2 Experiments 38
4.3 Results and Discussion 40
4.4 Conclusions 55

Reference 56

Independent Topics 61

국문 초록 70
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dc.formatapplication/pdf-
dc.format.extent8323036 bytes-
dc.format.mediumapplication/pdf-
dc.language.isoen-
dc.publisher서울대학교 대학원-
dc.subjectsilicon thin film-
dc.subjectcharged nanoparticles-
dc.subjectnonclassical crystallization-
dc.subjectICP-CVD-
dc.subjectsubstrate bias-
dc.subject.ddc620-
dc.titleEffect of Substrate Bias on Deposition Behavior of Charged Silicon Nanoparticles in ICP-CVD Process-
dc.title.alternative유도결합플라즈마를 이용한 화학기상증착 공정 중에 생성되는 하전된 실리콘 나노 입자의 증착 거동에 대한 기판 바이어스 효과-
dc.typeThesis-
dc.description.degreeDoctor-
dc.citation.pages83-
dc.contributor.affiliation공과대학 재료공학부-
dc.date.awarded2016-08-
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