3-Dimensional NAND flash memory having Tied Bit-line and Ground Select Transistor (TiGer)

Abstract

The demand for flash memory in mobile devices such as smart phone and pads, and digital cameras, portable music players is constantly increasing. Moreover, many hard disk drives in desktop computer are replaced by the solid state drives. This trend accelerates the scaling down of NAND flash memory. As NAND flash memory is scaled down, short channel effect and reliability problems become more severe and further scaling down is faced with process limitations. To overcome these problems, 3-D stacked NAND flash memory has been introduced for ultra-high-density storage device. Among the proposed structures, channel stacked array has most outstanding electrical characteristic, but has several drawbacks related with decoding difficulty, and additional process steps. In this dissertation, Channel STacked ARray (CSTAR) having Tied bit-line and Ground Select Transistor (TiGer) structure is proposed and investigated to solve problems of conventional channel stacked array. In case of CSTAR having TiGer, the stacked layers can be distinguished by addressing of common source line (CSL) and bit-line (BL) only. Since ground select transistors (GSTs) are tied with BLs, there are no ground select line (GSL) and GSL decoder. This is main feature of TiGer structure. To execute memory operations successfully, novel program operation scheme for TiGer structure is introduced because the GST of TiGer structure can be handled independently unlike conventional NAND flash memory. To verify the proposed operation scheme, TCAD simulation is performed. To fabricate the stacked array, process flow and several unit processes are investigated, and finally 4-stacked single crystalline Si nanowire with GAA structure is fabricated. Si/SiGe epitaxial growth, isotropic SiGe selective etching, stacked nanowire formation, and damascene gate formation are demonstrated, and memory operation for TiGer structure is verified by fabricated device.