Clock Polarity Assignment Methodologies for Designing High-Performance and Robust Clock Trees

Abstract

In modern synchronous circuits, the system relies on one single signal, namely, the clock signal. All data sampling of flip-flops rely on the timing of the clock signal. This makes clock trees, which deliver the clock signal to every clock sink in the whole system, one of the most active components on a chip, as it must switch without halting. Naturally, this makes clock trees a primary target of optimization for low power/high performance designs. First, bounded skew clock polarity assignment is explored. Buffers in the clock tree switch simultaneously as the clock signal switch, which causes power/ground supply voltage fluctuation. This phenomenon is referred to as clock noise and brings adverse effects on circuit robustness. Clock polarity assignment technique replaces some of the buffers in the clock trees with inverters. Since buffers draw larger current at the rising edge of the clock while inverters draw larger current at the falling edge, this technique can mitigate peak noise problem at the power/ground supply rails. Second, useful skew clock polarity assignment method is developed. Useful clock skew methodology allows consideration of individual clock skew restraints between each clock sinks, allowing further noise reduction by exploiting more time slack. Through experiments with ISPD 2010 clock network synthesis contest benchmark circuits, the results show that the proposed clock polarity algorithm is able to reduce the peak noise caused by clock buffers by 10.9% further over that of the global skew bound constrained polarity assignment while satisfying all setup and hold time constraints. Lastly, as multi-corner multi-mode (MCMM) design methodologies, process variations and clock gating techniques are becoming common place in advanced technology nodes, clock polarity assignment methods that mitigate these problems are devised. Experimental results indicate that the proposed methods successfully satisfy required design constraints imposed by such variations. In summary, this dissertation presents clock polarity assignments that considers useful clock skew, delay variations, MCMM design methodologies and clock gating techniques.