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A Temporal and Spatial Code Compression and Decompression Technique for Coarse-Grained Reconfigurable Architectures : 재구성 가능 아키텍처를 위한 시간적 공간적 코드 압축 및 압축해제 기법

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dc.contributor.advisorBernhard Egger-
dc.contributor.author이호찬-
dc.date.accessioned2017-07-14T02:36:36Z-
dc.date.available2017-07-14T02:36:36Z-
dc.date.issued2017-02-
dc.identifier.other000000141632-
dc.identifier.urihttps://hdl.handle.net/10371/122693-
dc.description학위논문 (석사)-- 서울대학교 대학원 : 컴퓨터공학부, 2017. 2. Bernhard, Egger.-
dc.description.abstractIn this thesis, we propose an efficient and lightweight configuration memory compression technique to reduce the space required to store the execution plan and enhance runtime energy efficiency for coarse-grained reconfigurable architectures. As the industry requires more flexibility to adapt the fast growth of applications, coarse-grained reconfigurable architectures have received more attention. However, the area and power overhead of the configuration memory that stores the execution plan of a loop kernel are significant and hinder a broader deployment of CGRA chips. To relieve this problem, we introduce a method to compress configuration memory by removing consecutive duplicated lines. Our compression technique uses two optimizations, spatial and temporal optimization, to generate more compression-friendly code. The temporal optimization sets control signals of the hardware entities in the CGRA to the same values of its neighboring lines and makes them as similar to them as possible without affecting the outcome of the computation. As a result, it minimizes the number of configuration changes for individual entities. The spatial optimization divides the configuration memory into sub-partitions to increase the potential of duplication of neighboring configuration lines. This thesis suggests two techniques, each in order to effectively apply spatial and temporal optimization. Decompression is performed by a simple hardware decoder logic that is able to decode lines with no additional latency and negligible area overhead. Experiments with 193 loop kernels extracted from thirty real-world applications show that the proposed compression technique achieves a memory reduction rate by almost 60% on average. The compression of unseen code accomplishes a memory reduction of over 45 % on average. As a result, our technique results in about a 35 to 70% reduction in energy consumption in the configuration memory in diverse types of experiments.-
dc.description.tableofcontentsChapter 1 Introduction 1
Chapter 2 Background 5
2.1 Coarse-grained Reconfigurable Architectures 5
2.2 Configuration Memory 7
2.3 Execution Model 10
2.4 Area and Energy Breakdown 12
Chapter 3 Related Work 13
Chapter 4 Configuration Memory Compression/Decompression 18
4.1 Code Compression 18
4.2 Decompression 19
4.3 Observation 21
Chapter 5 Code Optimization 23
5.1 Temporal Optimization 23
5.1.1 AMAP propagation 25
5.1.2 ASAP-ALAN propagation 27
5.1.3 Predicated Execution For Temporal Optimization 29
5.2 Spatial Optimization 29
Chapter 6 Memory Partitioning based on Statistical Analysis 32
6.1 Edit distance based Memory Partitioning 34
6.2 Bin-packing based Memory Partitioning 38
Chapter 7 Evaluation 41
7.1 Target Architectures and Benchmarks 41
7.2 Experimental methods 43
7.3 Compressibility on the degree of partitioning 43
7.4 Compression and energy reduction 44
7.5 Compressibility of trained. vs unseen code 45
Chapter 8 Conclusion 47
Bibliography 48
요약 53
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dc.formatapplication/pdf-
dc.format.extent3555730 bytes-
dc.format.mediumapplication/pdf-
dc.language.isoen-
dc.publisher서울대학교 대학원-
dc.subject재구성 가능 아키텍처의 압축 및 해제 기법-
dc.subject.ddc621-
dc.titleA Temporal and Spatial Code Compression and Decompression Technique for Coarse-Grained Reconfigurable Architectures-
dc.title.alternative재구성 가능 아키텍처를 위한 시간적 공간적 코드 압축 및 압축해제 기법-
dc.typeThesis-
dc.description.degreeMaster-
dc.citation.pages56-
dc.contributor.affiliation공과대학 컴퓨터공학부-
dc.date.awarded2017-02-
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