Power Optimization Techniques Applicable in Pre/Post Placement Stages for Modern System-on-Chips

Abstract

In this paper, we introduce two power optimization techniques applicable before and after placement stage. First, a new approach to the problem of allocating multi-bit flip-flops for data storage is presented. Previous approaches divide the allocation problem into two separate steps: (i) placing single-bit flip-flops under circuit timing constraints and (ii) minimizing the flip-flop and clock tree power by grouping single-bit flip-flops to form multi-bit flip-flops. Yet, there is no easy way to predict the result of step (ii) during step (i). In our approach, we place primary importance on the cost of power consumption. Consequently, we try to minimize power consumption by synthesizing multi-bit flip-flops first and then to place them later. For a number of benchmark circuits, it is shown that our approach of early consideration of synthesizing multi-bit flip-flops is very effective, reducing the clock power by 16.8% over that of the conventional method while satisfying all the timing constraints. The second work addresses a practical problem of optimizing the switch cells in power-gated modern System-on-Chips (SoCs) to save the unnecessary standby leakage under noise (i.e., IR-drop) constraint. Since power gating switch cells are physically directly connected to power rails, their overall allocation structure is synthesized in a stage before logic cell placement. Consequently, the allocation of switch cells in the pre-placement could lead to unnecessarily high standby leakage for modern designs. This work proposes a practical remedy for this problem at the post-placement stage. Specifically, for an initial design with a grid-based switch cell allocation, which is commonly used design methodology in industry, we propose a comprehensive solution to determining, for each switch cell, (i) if the cell can be removed or (ii) the type of switch cell for replacement so that the resulting total standby leakage of switch cells should be minimized under the noise constraint.We formulate the problem into a variant of weighted set cover problem and solve it efficiently by employing an approximate set cover algorithm. Through experiments with benchmark circuits in ISCAS89, openMSP430, and fpu, it is shown that our method is able to reduce the standby leakage by 35.0% and 13.9% over the initial designs and the designs produced by the previous switch cell optimization method in [9], respectively.